Manualsbrain.com
  1. Manuals
  2. Brands
  3. Intel
  4. N455
  5. User Manual

Intel N455 AU80610006237AA User Manual

Product codes
AU80610006237AA
Download
Page of 85
Functional Description
34
Datasheet
3.2.5.2.3
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel 
power, the backlight enable and the LVDS data timing delivery. In order to meet the 
panel power timing specification requirements, two signals, LVDD_EN
 
and BKLT_EN are 
provided to control the timing sequencing function of the panel and the backlight power 
supplies.
Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the 
panel. The set of timing parameters can vary from panel to panel vendor, provided that 
they stay within a predefined range of values. The panel VDD power, the backlight on/
off state and the LVDS clock and data lines are all managed by an internal power 
sequencer. 
A requested power-up sequence is only allowed to begin after the power cycle delay 
time requirement T4 is met.
Figure 3-4. Panel Power Sequencing
Table 3-18. Panel Power Sequencing Timing Parameters
Panel Power Sequence Timing Parameters
Min
Max
Name
Units
Spec Name
From
To
Vdd On
0.1 Vdd
0.9 Vdd
0
10
T1
ms
LVDS Active 
Vdd Stable On
LVDS Active
0
50
T2
ms
Backlight
LVDS Active
Backlight on
200
T5
ms
Backlight State 
Backlight Off
LVDS off
X
X
TX
ms
LVDS State
LVDS Off
Start power off
0
50
T3
ms
Power cycle Delay
Power Off
Power On 
Sequence Start
0
400
T4
ms
Power On Sequence from off state and
Power Off Sequence after full On
Panel VDD
Enable
Panel
BackLight
Enable
Clock/Data Lines
T1+T2
T5
T3
Valid
T4
Panel
On
Off
Off
TX
T4