Apple II User Manual

To save code, the subroutine entry address (minus 1) is pushed onto

the stack, high-order byte first. A 6502 RTS (return from subroutine)

is used to pop the address off the stack and into the 6502 PC (after

incrementing by 1). The net result is that the desired subroutine is

reached by executing a subroutine return instruction!

Opcode Subroutines:

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The register op routines make use of the 6502 'zero page indexed by X'

and 'indexed by X direct' addressing modes to access the specified

registers and indirect data. The 'result' of most register ops is left

in the specified register and can be sensed by subsequent branch

instructions, since the register specification is saved in the high-

order byte of R14. This specification is changed to indicate R0 (ACC)

for ADD and SUB instructions and R13 for the CPR (compare) instruction.

Normally the high-order R14 byte holds the 'prior result register'

index times 2 to account for the 2-byte SWEET 16 registers and the

LSB is zero. If ADD, SUB, or CPR instructions generate carries, then

this index is incremented, setting the LSB.

The SET instruction increments the PC twice, picking up data bytes in

the specified register. In accordance with 6502 convention, the

low-order data byte precedes the high-order byte.

Most SWEET 16 non-register ops are relative branches. The corresponding

subroutines determine whether or not the 'prior result' meets the

specified branch condition and if so, update the SWEET 16 PC by adding

the displacement value (-128 to +127 bytes).

The RTN op restores the 6502 register contents, pops the subroutine

return stack and jumps indirect through the SWEET 16 PC. This transfers

control to the 6502 at the instruction immediately following the

RTN instruction.

The BK op actually executes a 6502 break instruction (BRK), transferring

control to the interrupt handler.

Any number of subroutine levels may be implemented within SWEET 16 code

via the BS (Branch to Subroutine) and RS (Return from Subroutine)

instructions. The user must initialize and otherwise not disturb R12 if

the SWEET 16 subroutine capability is used since it is utilized as the

automatic return stack pointer.

Memory Allocation:

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The only storage that must be allocated for SWEET 16 variables are 32

consecutive locations in page zero for the SWEET 16 registers, four

locations to save the 6502 register contents, and a few levels of the

6502 subroutine return address stack. if you don't need to preserve the

6502 register contents, delete the SAVE and RESTORE subroutines and the

corresponding subroutine calls. This will free the four page zero

locations ASAV, XSAV, YSAV, and PSAV.