NEC PD750008 User Manual
226
µPD750008 USER'S MANUAL
Table 8-1. Status of the Hardware after a Reset (1/2)
Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is
generated.
Program counter (PC)
PSW
Stack pointer (SP)
Stack bank selection register (SBS)
Data memory (RAM)
General registers (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Basic
interval
timer/watch-
dog timer
interval
timer/watch-
dog timer
Timer
event
counter
event
counter
Timer
counter
counter
Clock timer
Serial
interface
interface
µPD750004
µPD750006,
µPD750008
µPD750008
µPD75P0016
Generation of a RESET signal
in a standby mode
in a standby mode
4 low-order bits at address
0000H in program memory are
set in PC bits 11 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 11 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
5 low-order bits at address
0000H in program memory are
set in PC bits 12 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 12 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
5 low-order bits at address
0000H in program memory are
set in PC bits 13 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 13 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
Held
0
0
Bit 6 at address 0000H in
program memory is set in RBE,
and bit 7 is set in MBE.
program memory is set in RBE,
and bit 7 is set in MBE.
Undefined
1000B
Held
Note
Held
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Held
0
0
Held
Carry flag (CY)
Skip flags (SK0 to SK2)
Interrupt status flags (IST0, IST1)
Bank enable flags (MBE, RBE)
Counter (BT)
Mode register (BTM)
Watchdog timer enable flag
(WDTM)
(WDTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT flip-flop
Counter (T1)
Modulo registers (TMOD1)
Mode register (TM1)
TOE1, TOUT flip-flop
Mode register (WM)
Shift register (SIO)
Operation mode register
(CSIM)
(CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Generation of a RESET signal
during operation
during operation
4 low-order bits at address
0000H in program memory are
set in PC bits 11 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 11 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
5 low-order bits at address
0000H in program memory are
set in PC bits 12 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 12 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
5 low-order bits at address
0000H in program memory are
set in PC bits 13 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
0000H in program memory are
set in PC bits 13 to 8, and the
data at address 0001H are set
in PC bits 7 to 0.
Undefined
0
0
Bit 6 at address 0000H in
program memory is set in RBE,
and bit 7 is set in MBE.
program memory is set in RBE,
and bit 7 is set in MBE.
Undefined
1000B
Undefined
Undefined
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Undefined
0
0
Undefined
Hardware