Motorola MVME187 User Manual

Setting Environment to Bug/Operating System

A-13

F-Page (VMEbus A24) Enable 
[Y/N]

Y

Yes, Enable the F-Page Address 
Decoder. 

F-Page (VMEbus A24) Control

02

Works the same as Slave Control #1. 
Default is $02. 

ROM Speed Bank A Code 
ROM Speed Bank B Code 

05
05

Used to set up the ROM speed. 
Default is $05 = 165 ns (25 MHz 
MVME187) or $04=145 ns (33 MHz 
MVME187).

Static RAM Speed Code

01

Used to set up the SRAM speed. 
Default is $01 = 125 ns (25 MHz 
MVME187) or $00=115 ns (33 MHz 
MVME187).

PCC2 Vector Base 
VMEC2 Vector Base #1 
VMEC2 Vector Base #2 

05 
06 
07 

Base interrupt vector for the 
component speciÞed. Default: 
PCCchip2 = $05, VMEchip2 Vector 1 = 
$06, VMEchip2 Vector 2 = $07. 

VMEC2 GCSR Group 
Base Address

CE

SpeciÞes the group address 
($FFFFXX00) in Short I/O for this 
board. Default = $CE. 

VMEC2 GCSR Board Base 
Address

00

SpeciÞes the base address 
($FFFFCEX0) in Short I/O for this 
board. Default = $00. 

VMEbus Global Time Out Code

01

This controls the VMEbus timeout 
when this MVME187 is the system 
controller. Default $01 = 64 

µ

s. 

Local Bus Time Out Code

00

This controls the local bus timeout. 
Default $00 = 8 

µ

s. 

VMEbus Access Time Out Code

02

This controls the local bus to VMEbus 
access timeout. Default $02 = 32 ms.