Motorola MVME187 User Manual
Memory Maps
2-25
2
Table 2-5. Local Bus Memory Map
Address
Range
Devices Accessed
Port Size
Size
Software
Cache
Inhibit
Notes
$00000000 -
DRAMSIZE
DRAMSIZE
User programmable
(onboard DRAM)
(onboard DRAM)
D32
DRAMSIZE
N
1, 2
DRAMSIZE
- $FF7FFFFF
- $FF7FFFFF
User programmable
(VMEbus)
(VMEbus)
D32/D16
3GB
?
3, 4
$FF800000 -
$FFBFFFFF
$FFBFFFFF
ROM
D32
4MB
N
1
$FFC00000 -
$FFDFFFFF
$FFDFFFFF
Reserved
--
2MB
--
5
$FFE00000 -
$FFE1FFFF
$FFE1FFFF
SRAM
D32
128KB
N
--
$FFE20000 -
$FFEFFFFF
$FFEFFFFF
SRAM (repeated)
D32
896KB
N
--
$FFF00000 -
$FFFEFFFF
$FFFEFFFF
Local I/O devices
(refer to next table)
(refer to next table)
D32-D8
1MB
Y
3
$FFFF0000 -
$FFFFFFFF
$FFFFFFFF
User programmable
(VMEbus A16)
(VMEbus A16)
D32/D16
64KB
?
2, 4
Notes
1. Onboard EPROM appears at $00000000 - $003FFFFF following a local bus
1. Onboard EPROM appears at $00000000 - $003FFFFF following a local bus
reset. The EPROM appears at 0 until the ROM0 bit is cleared in the
VMEchip2. The ROM0 bit is located at address $FFF40030 bit 20. The
EPROM must be disabled at 0 before the DRAM is enabled. The VMEchip2
and DRAM map decoders are disabled by a local bus reset.
VMEchip2. The ROM0 bit is located at address $FFF40030 bit 20. The
EPROM must be disabled at 0 before the DRAM is enabled. The VMEchip2
and DRAM map decoders are disabled by a local bus reset.
2. This area is user-programmable. The suggested use is shown in the table.
The DRAM decoder is programmed in the MEMC040 or MCECC chip, and
the local-to-VMEbus decoders are programmed in the VMEchip2.
the local-to-VMEbus decoders are programmed in the VMEchip2.
3. Size is approximate.
4. Cache inhibit depends on devices in area mapped.
5. This area is not decoded. If these locations are accessed and the local bus
4. Cache inhibit depends on devices in area mapped.
5. This area is not decoded. If these locations are accessed and the local bus
timer is enabled, the cycle times out and is terminated by a TEA signal.