Motorola MVME1X7P User Manual
2-64
Computer Group Literature Center Web Site
VMEchip2
2
DLPE
If this bit is set, the DMAC has received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared when the DMAC is enabled.
status indicated a parity error during a DRAM data
transfer. This bit is cleared when the DMAC is enabled.
DLBE
If this bit is set, the DMAC has received a TEA and no
additional status was provided. This bit is cleared when
the DMAC is enabled.
additional status was provided. This bit is cleared when
the DMAC is enabled.
MLTO
If this bit is set, the MPU has received a TEA and the
status indicated a local bus time-out. This bit is cleared by
writing a 1 to the MCLR bit in this register.
status indicated a local bus time-out. This bit is cleared by
writing a 1 to the MCLR bit in this register.
Programming the Tick and Watchdog Timers
The VMEchip2 has two 32-bit tick timers and one watchdog timer. This
section provides addresses and bit level descriptions of the prescaler, tick
timer, watchdog timer registers, and various other timer registers.
section provides addresses and bit level descriptions of the prescaler, tick
timer, watchdog timer registers, and various other timer registers.
VMEbus Arbiter Time-Out Control Register
This register controls the VMEbus arbiter time-out timer.
ARBTO
When this bit is high, the VMEbus grant time-out timer is
enabled. When this bit is low, the VMEbus grant timer is
disabled. When the timer is enabled and the arbiter does
not receive a BBSY signal within 256
enabled. When this bit is low, the VMEbus grant timer is
disabled. When the timer is enabled and the arbiter does
not receive a BBSY signal within 256
µ
s after a grant is
issued, the arbiter asserts BBSY and removes the grant.
The arbiter then rearbitrates any pending requests.
The arbiter then rearbitrates any pending requests.
ADR/SIZ
$FFF4004C (8 bits [1 used] of 32)
BIT
31
30
29
28
27
26
25
24
NAME
ARBTO
OPER
R/W
RESET
0 PS