Motorola MVME1X7P User Manual
2-66
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VMEchip2
2
VME Access, Local Bus, and Watchdog Time-out Control Register
WDTO
These bits define the watchdog time-out period:
LBTO
These bits define the local bus time-out value. The timer
begins timing when TS is asserted on the local bus. If TA
or TAE is not asserted before the timer times out, a TEA
signal is sent to the local bus. The timer is disabled if the
transfer is bound for the VMEbus.
begins timing when TS is asserted on the local bus. If TA
or TAE is not asserted before the timer times out, a TEA
signal is sent to the local bus. The timer is disabled if the
transfer is bound for the VMEbus.
VATO
These bits define the VMEbus access time-out value.
When a transaction is headed to the VMEbus and the
VMEchip2 is not the current VMEbus master, the access
timer begins timing. If the VMEchip2 has not received
bus mastership before the timer times out and the
transaction is not write posted, a TEA signal is sent to the
local bus. If the transaction is write posted, a write post
error interrupt is sent to the local bus interrupter.
When a transaction is headed to the VMEbus and the
VMEchip2 is not the current VMEbus master, the access
timer begins timing. If the VMEchip2 has not received
bus mastership before the timer times out and the
transaction is not write posted, a TEA signal is sent to the
local bus. If the transaction is write posted, a write post
error interrupt is sent to the local bus interrupter.
ADR/SIZ
$FFF4004C (8 bits of 32)
BIT
15
14
13
12
11
10
9
8
NAME
VATO
LBTO
WDTO
OPER
R/W
R/W
R/W
RESET
0 PS
0 PS
0 PS
Bit Encoding
Time-out
Bit Encoding
Time-out
0
512
µ
s
8
128 ms
1
1 ms
9
256 ms
2
2 ms
10
512 ms
3
4 ms
11
1 s
4
8 ms
12
4 s
5
16 ms
13
16 s
6
32 ms
14
32 s
7
64 ms
15
64 s
0
8
µ
s
2
256
µ
s
1
64
µ
s
3
The timer is disabled
0
64
µ
s
2
32
ms
1
1
ms
3
The timer is disabled