Motorola MVME1X7P User Manual
LCSR Programming Model
http://www.motorola.com/computer/literature
2-81
2
Local Bus Interrupter Enable Register (bits 24-31)
This register is the local bus interrupter enable register. When an enable bit
is high, the corresponding interrupt is enabled. When an enable bit is low,
the corresponding interrupt is disabled. The enable bit does not clear
edge-sensitive interrupts or prevent the flip-flop from being set. If
necessary, edge-sensitive interrupters should be cleared to remove any old
interrupts and then re-enabled.
is high, the corresponding interrupt is enabled. When an enable bit is low,
the corresponding interrupt is disabled. The enable bit does not clear
edge-sensitive interrupts or prevent the flip-flop from being set. If
necessary, edge-sensitive interrupters should be cleared to remove any old
interrupts and then re-enabled.
ETIC1
Enable tick timer 1 interrupt.
ETIC2
Enable tick timer 2 interrupt.
EVI1E
Enable VMEbus IRQ1 edge-sensitive interrupt.
EPE
Not used on MVME1x7P.
EMWP
Enable VMEbus master write post error interrupt.
ESYSF
Enable VMEbus SYSFAIL interrupt.
EAB
Not used on MVME1x7P.
EACF
Enable VMEbus ACFAIL interrupt.
ADR/SIZ
$FFF4006C (8 bits of 32)
BIT
31
30
29
28
27
26
25
24
NAME
EACF
EAB
ESYSF
EMWP
EPE
EVI1E
ETIC2
ETIC1
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL