Motorola MVME1X7P User Manual
2-82
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VMEchip2
2
Local Bus Interrupter Enable Register (bits 16-23)
This register is the local bus interrupter enable register. When an enable bit
is high, the corresponding interrupt is enabled. When an enable bit is low,
the corresponding interrupt is disabled. The enable bit does not clear
edge-sensitive interrupts or prevent the flip-flop from being set. If
necessary, edge-sensitive interrupters should be cleared to remove any old
interrupts and then re-enabled.
is high, the corresponding interrupt is enabled. When an enable bit is low,
the corresponding interrupt is disabled. The enable bit does not clear
edge-sensitive interrupts or prevent the flip-flop from being set. If
necessary, edge-sensitive interrupters should be cleared to remove any old
interrupts and then re-enabled.
ELM0
Enable GCSR LM0 interrupt.
ELM1
Enable GCSR LM1 interrupt.
ESIG0
Enable GCSR SIG0 interrupt.
ESIG1
Enable GCSR SIG1 interrupt.
ESIG2
Enable GCSR SIG2 interrupt.
ESIG3
Enable GCSR SIG3 interrupt.
EDMA
Enable DMAC interrupt.
EVIA
VMEbus interrupter acknowledge interrupt.
ADR/SIZ
$FFF4006C (8 bits of 32)
BIT
23
22
21
20
19
18
17
16
NAME
EVIA
EDMA
ESIG3
ESIG2
ESIG1
ESIG0
ELM1
ELM0
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL
0 PSL