Motorola MVME1X7P User Manual
Functional Description
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3-9
3
Tick Timer
The PCCchip2 includes two 32-bit general purpose tick timers. The tick
timers run on a 1MHz clock which is derived from the processor clock by
a prescaler.
timers run on a 1MHz clock which is derived from the processor clock by
a prescaler.
Each tick timer has a 32-bit counter, a 32-bit compare register, and a clear-
on-compare enable bit. The counter is readable and writable at any time.
These timers can be used to generate interrupts at various rates or the
counters can be read at various times for interval timing. There are two
modes of operation for these timers: free-running and clear-on-compare.
on-compare enable bit. The counter is readable and writable at any time.
These timers can be used to generate interrupts at various rates or the
counters can be read at various times for interval timing. There are two
modes of operation for these timers: free-running and clear-on-compare.
In free-running mode, the timers have a resolution of 1
µ
s and roll over
after the count reaches the maximum value $FFFFFFFF. The rollover
period for the timers is 71.6 minutes.
period for the timers is 71.6 minutes.
When the counter is enabled in the clear-on-compare mode, it increments
every 1
every 1
µ
s until the counter value matches the value in the compare
register. When a match occurs, the counter is cleared.
When a match occurs, in either mode, an interrupt is sent to the Local Bus
interrupter and the overflow counter is incremented. An interrupt to the
Local Bus is only generated if the tick timer interrupt is enabled by the
Local Bus interrupter. The overflow counter can be cleared by writing a
one to the overflow clear bit.
interrupter and the overflow counter is incremented. An interrupt to the
Local Bus is only generated if the tick timer interrupt is enabled by the
Local Bus interrupter. The overflow counter can be cleared by writing a
one to the overflow clear bit.