Motorola MVME1X7P User Manual
Programming Model
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Programming Model
This section defines the programming model for the control and status
registers (CSR) in the PCCchip2. The base address of the CSR is
$FFF42000. The PCCchip2 control and status registers can be accessed as
bytes (8 bits), two-bytes (16 bits), or four-bytes(32 bits). The possible
operations for each bit in the CSR are as follows:
registers (CSR) in the PCCchip2. The base address of the CSR is
$FFF42000. The PCCchip2 control and status registers can be accessed as
bytes (8 bits), two-bytes (16 bits), or four-bytes(32 bits). The possible
operations for each bit in the CSR are as follows:
The possible states of the bits after local and power-up reset are as defined
below.
below.
A summary of the PCCchip2 CSR is shown in Table 6-2.
R
This bit is a read only status bit.
R/W
This bit is readable and writable.
W/AC This bit can be set and it is automatically cleared.
This bit can also be read.
C
Writing a one to this bit clears this bit or another bit.
This bit reads zero.
This bit reads zero.
S
Writing a one to this bit sets this bit or another bit.
This bit reads zero.
This bit reads zero.
0
This bit is read only. It always reads as 0.
P
The bit is affected by power-up reset.
L
The bit is affected by local reset.
X
The bit is not affected by reset.
V
The effect of reset on this bit is variable.
0
The bit is always 0.
1
The bit is always 1.