Motorola MVME1X7P User Manual
3-48
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PCCchip2
3
Interrupt Priority Level Register
IPL2-IPL0
Interrupt Priority Level - These bits reflect the priority-
encoded interrupt request level. This level is a
combination of the PCCchip2 interrupt requests and the
interrupt requests driven onto the EIPL2-EIPL0 pins.
encoded interrupt request level. This level is a
combination of the PCCchip2 interrupt requests and the
interrupt requests driven onto the EIPL2-EIPL0 pins.
Note that when the C040 bit is cleared, external devices
can drive EIPL2-EIPL0 with their interrupt requests.
can drive EIPL2-EIPL0 with their interrupt requests.
When C040 is set, the PCCchip2 drives EIPL2-EIPL0
with its interrupt requests. In this case (C040 set), IPL2-
IPL0 only reflect PCCchip2 interrupt requests. The IPL
bits are encoded as shown below:
with its interrupt requests. In this case (C040 set), IPL2-
IPL0 only reflect PCCchip2 interrupt requests. The IPL
bits are encoded as shown below:
ADR/SIZ
$FFF4203E (8 bits)
BIT
15
14
13
12
11
10
9
8
NAME
IPL2
IPL1
IPL0
OPER
R
R
R
R
R
R
R
R
RESET
0
0
0
0
0
X
X
X
IPL2
IPL1
IPL0
Priority Level
Comments
0
0
0
0
No Interrupt
0
0
1
1
Lowest Level
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Highest Level