Motorola MVME1X7P User Manual
Programming Model
http://www.motorola.com/computer/literature
3-49
3
Interrupt Mask Level Register
MSK2-MSK0 Interrupt Mask Level - The interrupt mask level bits
determine the level which must be exceeded by IPL2-
IPL0 in order for the PCCchip2 to assert its INT pin. The
MSK bits are encoded as follows:
IPL0 in order for the PCCchip2 to assert its INT pin. The
MSK bits are encoded as follows:
ADR/SIZ
$FFF4203F (8 bits)
BIT
7
6
5
4
3
2
1
0
NAME
MSK2
MSK1
MSK0
OPER
R
R
R
R
R
R/W
R/W
R/W
RESET
0
0
0
0
0
1 PL
1 PL
1 PL
MSK2
MSK1
MSK0
Priority Level
Comments
0
0
0
0
Lowest Level
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Highest Level