Motorola MVME1X7P User Manual
4-8
Computer Group Literature Center Web Site
MCECC Functions
4
Error Logging
ECC error logging is facilitated by the Petra MCECC sector because of its
internal latches. When an error (single- or double-bit) occurs in the
DRAMs to which the MCECC sector is connected, it freezes the address
of the error and the syndrome bits associated with the data that is in error.
Each MCECC sector segment performs this logging function
independently of the other. Once the MCECC sector has logged an error,
it does not log any new errors that occur until the ERRLOG control/status
bit has been cleared by software.
internal latches. When an error (single- or double-bit) occurs in the
DRAMs to which the MCECC sector is connected, it freezes the address
of the error and the syndrome bits associated with the data that is in error.
Each MCECC sector segment performs this logging function
independently of the other. Once the MCECC sector has logged an error,
it does not log any new errors that occur until the ERRLOG control/status
bit has been cleared by software.
Scrub
The MCECC sector contains programmable registers and circuitry to
implement the memory scrubbing function. Programmable registers
determine how often the entire DRAM is scrubbed. During a scrub, the
scrubber holds the memory for a programmable amount of time and then
releases it for the local bus, or for a refresher if one of them is requesting
local bus mastership. The scrubber then refrains from using the DRAM
again for a programmable amount of time. Each scrub cycle is made up of
a full 39-bit read of DRAM, a correction of any single-bit errors, and a
write of the full 39 corrected bits back to the same location. If a single- or
double-bit error occurs and if such interrupts are enabled in the control
register, the local bus master is notified. A software bit is available to
disable the read portion of the scrub cycle.
implement the memory scrubbing function. Programmable registers
determine how often the entire DRAM is scrubbed. During a scrub, the
scrubber holds the memory for a programmable amount of time and then
releases it for the local bus, or for a refresher if one of them is requesting
local bus mastership. The scrubber then refrains from using the DRAM
again for a programmable amount of time. Each scrub cycle is made up of
a full 39-bit read of DRAM, a correction of any single-bit errors, and a
write of the full 39 corrected bits back to the same location. If a single- or
double-bit error occurs and if such interrupts are enabled in the control
register, the local bus master is notified. A software bit is available to
disable the read portion of the scrub cycle.
Refresh
The MCECC sector provides refresh control for the DRAM. It performs a
single CAS-before-RAS refresh cycle to the two DRAM blocks
approximately once every 15.6
single CAS-before-RAS refresh cycle to the two DRAM blocks
approximately once every 15.6
µ
s.