Motorola MVME1X7P User Manual
4-10
Computer Group Literature Center Web Site
MCECC Functions
4
Programming Model
This section defines the programming model for the control and status
registers (CSRs) in the MCECC sector. The base address of the CSRs is
hard-coded to the address $FFF43000 for the MCECC sector on the first
mezzanine board and to $FFF43100 for the MCECC sector on the second
mezzanine board.
registers (CSRs) in the MCECC sector. The base address of the CSRs is
hard-coded to the address $FFF43000 for the MCECC sector on the first
mezzanine board and to $FFF43100 for the MCECC sector on the second
mezzanine board.
Note that several bits in the register map have changed in functionality
from the MCECC ASIC pair. In most cases these bits were defined to be
nonoperational in the MCECC model, but were also defined as to their
original intent. This specification entirely omits those bit definitions.
from the MCECC ASIC pair. In most cases these bits were defined to be
nonoperational in the MCECC model, but were also defined as to their
original intent. This specification entirely omits those bit definitions.
The possible operations for each bit in the CSR are as follows:
The possible states of the bits after local, software, and power-up reset are
as defined below.
as defined below.
R
The bit is a read-only status bit.
R/W
The bit is readable and writable.
R/C
This status bit is cleared by writing a 1 to it.
C
Writing a 0 to the bit clears it or another bit. This bit reads zero.
S
Writing a 1 to the bit sets it or another bit. This bit reads 0.
P
The bit is affected by power-up reset.
L
The bit is affected by local reset.
S
The bit is affected by software reset. (Writing $0F to the Chip
ID register)
ID register)
X
The bit is not affected by reset.
V
The effect of reset on this bit is variable.