Motorola MVME1X7P User Manual
4-30
Computer Group Literature Center Web Site
MCECC Functions
4
Error Syndrome Register
S6-S0
Bits SYNDROME6-0 reflect the syndrome value at the last
logging of an error. The seven-bit code indicates the
position of the data error. When all the bits are 0, there is
no error. Note that if the logged error was non-
correctable, then these bits are meaningless (refer to the
logging of an error. The seven-bit code indicates the
position of the data error. When all the bits are 0, there is
no error. Note that if the logged error was non-
correctable, then these bits are meaningless (refer to the
section).
Defaults Register 1
It is not recommended that non-test software write to this register.
RSIZ2-RSIZ0
Bits RSIZ2-RSIZ0 determine the size of the DRAM array
that is assumed by the MCECC. They control the size as
follows:
that is assumed by the MCECC. They control the size as
follows:
ADR/SIZ
1st $FFF43070/2nd $FFF43170 (16-bits)
BIT
31
30
29
28
27
26
25
24
NAME
0
S6
S5
S4
S3
S2
S1
S0
OPER
R
R
R
R
R
R
R
R
RESET
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
ADR/SIZ
1st $FFF43074/2nd $FFF43174 (8-bits)
BIT
31
30
29
28
27
26
25
24
NAME
RWB7
RWB6
FSTRD
SELI1
SELI0
RSIZ2
RSIZ1
RSIZ0
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0 PL
V PLS
V PLS
V PLS
V PLS
V PLS
V PLS
V PLS