Motorola MVME1X7P User Manual
Programming Interfaces
http://www.motorola.com/computer/literature
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The MVME177P implements primary and secondary backup sources. You
can select from +5V standby power, the onboard battery, or both.
can select from +5V standby power, the onboard battery, or both.
The jumpers and configuration switches for the MVME167P and
MVME177P are described in Chapter 1 of the Installation and Use manual
for the respective boards.
MVME177P are described in Chapter 1 of the Installation and Use manual
for the respective boards.
Onboard SDRAM
MVME167P boards are built with 16MB-64MB synchronous DRAM
(SDRAM). MVME177P boards are built with 16MB-128MB SDRAM.
The MVME1X7P may have the SDRAM configured to model 4MB, 8MB,
16MB, 32MB, 64MB, or 128MB of ECC-protected DRAM.
(SDRAM). MVME177P boards are built with 16MB-128MB SDRAM.
The MVME1X7P may have the SDRAM configured to model 4MB, 8MB,
16MB, 32MB, 64MB, or 128MB of ECC-protected DRAM.
In addition to the onboard SDRAM, an additional mezzanine (of the type
used on previous MVME1X7 boards) can be plugged in to provide up to
128MB of additional DRAM. All DRAM has ECC protection.
used on previous MVME1X7 boards) can be plugged in to provide up to
128MB of additional DRAM. All DRAM has ECC protection.
The SDRAM map decoder can be programmed to accommodate different
base address(es) and sizes of mezzanine boards. The onboard SDRAM is
disabled by a Local Bus reset; it must be programmed in order for you to
access it.
base address(es) and sizes of mezzanine boards. The onboard SDRAM is
disabled by a Local Bus reset; it must be programmed in order for you to
access it.
Most DRAM devices require some number of access cycles before the
DRAMs are fully operational. Normally this requirement is met by the
onboard refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
DRAMs are fully operational. Normally this requirement is met by the
onboard refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
Detailed programming information is available in the chapters on the
memory options.
memory options.