Motorola MVME1X7P User Manual
1-12
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Programming Issues
1
Battery-Backed-Up RAM and Clock
Although the M48T58-70 RAM and clock chip is an 8-bit device, the
interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses
to the M48T58. No interrupts are generated by the clock. Refer to
interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses
to the M48T58. No interrupts are generated by the clock. Refer to
and to the M48T58 data sheet for detailed programming
guidance and battery life information.
VMEbus Interface
The VMEbus interface is implemented with an ASIC called the
VMEchip2. The VMEchip2 includes:
VMEchip2. The VMEchip2 includes:
❏
Two tick timers
❏
A watchdog timer
❏
Programmable map decoders for the master and slave interfaces
❏
A VMEbus to/from local bus DMA controller
❏
A VMEbus to/from local bus non-DMA programmed access
interface
interface
❏
A VMEbus interrupter, a VMEbus system controller, a VMEbus
interrupt handler, and a VMEbus requester
interrupt handler, and a VMEbus requester
Processor-to-VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA
transfers to the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT,
or D64/MBLT.
transfers to the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT,
or D64/MBLT.
Refer to
for detailed programming information.
I/O Interfaces
The MVME167P and MVME177P single-board computers provide
onboard I/O for many system applications. The I/O functions include serial
ports, parallel (printer) port, Ethernet transceiver interface, and SCSI mass
storage interface.
onboard I/O for many system applications. The I/O functions include serial
ports, parallel (printer) port, Ethernet transceiver interface, and SCSI mass
storage interface.