Motorola MVME1X7P User Manual
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Programming Issues
1
ensure that data shared by multiple processors is kept in un-cached
memory. The software must also mark all onboard I/O areas as cache
inhibited and serialized.
memory. The software must also mark all onboard I/O areas as cache
inhibited and serialized.
Cache Coherency (MVME177P)
The MVME177P’s MC68060 processor has the ability to watch the
external bus during accesses by other bus masters, maintaining coherency
between the MC68060’s caches and external memory systems.To
maintain cache coherency, the MC68060 provides automatic snoop-
invalidation when it is not the bus master. When an external cycle is
marked as snoopable, the bus snooper checks the caches and invalidates
the matching data.
external bus during accesses by other bus masters, maintaining coherency
between the MC68060’s caches and external memory systems.To
maintain cache coherency, the MC68060 provides automatic snoop-
invalidation when it is not the bus master. When an external cycle is
marked as snoopable, the bus snooper checks the caches and invalidates
the matching data.
Unlike the MC68040, the MC68060 cannot source or sink cache data
during alternate bus master accesses. Therefore, the MVME177 uses a
single snoop control line – SC1. Snoop control bits for SC0 must be set to
0.
during alternate bus master accesses. Therefore, the MVME177 uses a
single snoop control line – SC1. Snoop control bits for SC0 must be set to
0.
MC68060 cache coherency and bus snooping capabilities are described in
the M68060 Microprocessors User’s Manual, in the sections on Cache
Coherency and Bus Snooping Operation.
the M68060 Microprocessors User’s Manual, in the sections on Cache
Coherency and Bus Snooping Operation.