Motorola MVME1X7P User Manual
Functional Blocks
http://www.motorola.com/computer/literature
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have been accessed. This enhances the portability of software because it
allows software to run on the system regardless of the physical
organization of global memory.
allows software to run on the system regardless of the physical
organization of global memory.
Using the local bus map decoder attribute register, the AM code that the
master places on the VMEbus can be programmed under software control.
master places on the VMEbus can be programmed under software control.
The VMEchip2 includes a software-controlled VMEbus access timer. It
starts ticking when the chip is requested to do a VMEbus data transfer or
an interrupt acknowledge cycle. The timer stops ticking once the chip has
started the data transfer on the VMEbus. If the data transfer does not begin
before the timer times out, the timer drives the local bus error signal, and
sets the appropriate status bit in the Local Control and Status Register
(LCSR). Using control bits in the LCSR, the timer can be disabled, or it
can be enabled to drive the local bus error signal after 64
starts ticking when the chip is requested to do a VMEbus data transfer or
an interrupt acknowledge cycle. The timer stops ticking once the chip has
started the data transfer on the VMEbus. If the data transfer does not begin
before the timer times out, the timer drives the local bus error signal, and
sets the appropriate status bit in the Local Control and Status Register
(LCSR). Using control bits in the LCSR, the timer can be disabled, or it
can be enabled to drive the local bus error signal after 64
µ
s, 1 ms, or 32
ms.
The VMEchip2 includes a software-controlled VMEbus write post timer.
It starts ticking when a data transfer to the VMEbus is write posted. The
timer stops ticking once the chip has started the data transfer on the
VMEbus. If this does not happen before the timer times out, the chip aborts
the write posted cycle and sends an interrupt to the local bus interrupter. If
the write post bus error interrupt is enabled in the local bus interrupter, the
local processor is interrupted to indicate a write post time-out has occurred.
The write post timer has the same timing as the VMEbus access timer.
It starts ticking when a data transfer to the VMEbus is write posted. The
timer stops ticking once the chip has started the data transfer on the
VMEbus. If this does not happen before the timer times out, the chip aborts
the write posted cycle and sends an interrupt to the local bus interrupter. If
the write post bus error interrupt is enabled in the local bus interrupter, the
local processor is interrupted to indicate a write post time-out has occurred.
The write post timer has the same timing as the VMEbus access timer.
Local-Bus-to-VMEbus Requester
The requester provides all the signals necessary to allow the local-bus-to-
VMEbus master to request and be granted use of the VMEbus. The chip
connects to all signals that a VMEbus requester is required to drive and
monitor.
VMEbus master to request and be granted use of the VMEbus. The chip
connects to all signals that a VMEbus requester is required to drive and
monitor.
Requiring no external jumpers, the chip provides the means for software to
program the requester to request the bus on any one of the four bus request
levels, automatically establishing the bus grant daisy-chains for the three
inactive levels.
program the requester to request the bus on any one of the four bus request
levels, automatically establishing the bus grant daisy-chains for the three
inactive levels.