Motorola MVME1X7P User Manual
Functional Blocks
http://www.motorola.com/computer/literature
2-9
2
VMEbus-to-Local-Bus Interface
The VMEbus-to-local-bus interface allows an off-board VMEbus master
access to onboard resources. The VMEbus-to-local-bus interface includes
the VMEbus slave, write post buffer, and local bus master.
access to onboard resources. The VMEbus-to-local-bus interface includes
the VMEbus slave, write post buffer, and local bus master.
Adhering to the IEEE 1014-87 VMEbus standard, the slave can withstand
address-only cycles, as well as address pipelining, and respond to
unaligned transfers. Using programmable map decoders, it can be
configured to provide the following VMEbus capabilities:
address-only cycles, as well as address pipelining, and respond to
unaligned transfers. Using programmable map decoders, it can be
configured to provide the following VMEbus capabilities:
Addressing capabilities:
A24, A32
Data transfer capabilities:
D08(EO), D16, D32, D8/BLT,
D16/BLT, D32/BLT, D64/BLT
(BLT = block transfer)
D16/BLT, D32/BLT, D64/BLT
(BLT = block transfer)
The slave can be programmed to perform write posting operations. When
in this mode, the chip latches incoming data and addressing information
into a staging FIFO and then acknowledges the VMEbus write transfer by
asserting DTACK
in this mode, the chip latches incoming data and addressing information
into a staging FIFO and then acknowledges the VMEbus write transfer by
asserting DTACK
∗
. The chip then requests control of the local bus and
independently accesses the local resource after it has been granted the local
bus. The write-posting pipeline is two deep in non-block transfer mode and
16 deep in block transfer mode.
bus. The write-posting pipeline is two deep in non-block transfer mode and
16 deep in block transfer mode.
To significantly improve the access time of the slave when it responds to
a VMEbus block read cycle, the VMEchip2 contains a 16 four-byte deep
read-ahead pipeline. When responding to a block read cycle, the chip
performs block read cycles on the local bus to keep the FIFO buffer full.
Data for subsequent transfers is then retrieved from the on-chip buffer,
significantly improving the response time of the slave in block transfer
mode.
a VMEbus block read cycle, the VMEchip2 contains a 16 four-byte deep
read-ahead pipeline. When responding to a block read cycle, the chip
performs block read cycles on the local bus to keep the FIFO buffer full.
Data for subsequent transfers is then retrieved from the on-chip buffer,
significantly improving the response time of the slave in block transfer
mode.
The VMEchip2 includes an on-chip map decoder that allows software to
configure the global addressing range of onboard resources. The decoder
allows the local address range to be partitioned into two separate banks,
each with its own start and end address (in increments of 64KB), as well
as setting each bank’s address modifier codes, write post enable, and snoop
enable.
configure the global addressing range of onboard resources. The decoder
allows the local address range to be partitioned into two separate banks,
each with its own start and end address (in increments of 64KB), as well
as setting each bank’s address modifier codes, write post enable, and snoop
enable.