Soyo SY-K7VEMPRO User Manual
Motherboard Description
SY-K7VEMPRO
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enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to
minimize snoop overhead. In addition, advanced features are supported
such as snoop ahead, snoop filtering, L1 write-back forward to PCI master,
and L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read
caching mechanisms are also implemented for further improvement of
over all system performance.
The 352-pin Ball Grid Array VT82C686B PCI to ISA bridge supports four
levels (double words) of line buffers, type F DMA transfers and delay
transaction to allow efficient PCI bus utilization The VT82C686B also
includes an integrated keyboard controller with PS/2 mouse support,
integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter/
gather capability and extension to UltraDMA-33/66 for 33/66 MB/sec
transfer rate, integrated USB interface with root Hub and two function
ports with built-in physical layer transceivers, Distributed DMA supports,
and On Now/ ACPI compliant advanced configuration and power
management interface.
For sophisticated power management, the Via 8361 provides independent
clock stop control for the CPU/SDRAM, PCI, and AGP buses and
Dynamic CKE control for powering down of the SDRAM. A separate
suspend-well plane is implemented for the SDRAM control signals for
Suspend-to-DRAM operation. Coupled with the VT82C686B south bridge
chip, a complete power conscious PC motherboard can be implemented
with no external TTLs.
The Via 8361 chipset is ideal for high performance, high quality, high
energy efficient and high integration desktop AGP / PCI computer
systems.
Memory-Read-Multiple and Memory-Write-Invalid commands to
minimize snoop overhead. In addition, advanced features are supported
such as snoop ahead, snoop filtering, L1 write-back forward to PCI master,
and L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read
caching mechanisms are also implemented for further improvement of
over all system performance.
The 352-pin Ball Grid Array VT82C686B PCI to ISA bridge supports four
levels (double words) of line buffers, type F DMA transfers and delay
transaction to allow efficient PCI bus utilization The VT82C686B also
includes an integrated keyboard controller with PS/2 mouse support,
integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter/
gather capability and extension to UltraDMA-33/66 for 33/66 MB/sec
transfer rate, integrated USB interface with root Hub and two function
ports with built-in physical layer transceivers, Distributed DMA supports,
and On Now/ ACPI compliant advanced configuration and power
management interface.
For sophisticated power management, the Via 8361 provides independent
clock stop control for the CPU/SDRAM, PCI, and AGP buses and
Dynamic CKE control for powering down of the SDRAM. A separate
suspend-well plane is implemented for the SDRAM control signals for
Suspend-to-DRAM operation. Coupled with the VT82C686B south bridge
chip, a complete power conscious PC motherboard can be implemented
with no external TTLs.
The Via 8361 chipset is ideal for high performance, high quality, high
energy efficient and high integration desktop AGP / PCI computer
systems.
VT82C686B
The VT82C686B PSIPC (PCI Super-I/O integrated Peripheral Controller)