Cypress CY7C64013C User Manual
CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 34 of 51
USB Status and Control
ADDRESS 0x1F
Bits[2..0] : Control Action
Set to control action as per Table 17-1.The three control bits allow the upstream port to be driven manually by firmware.
For normal USB operation, all of these bits must be cleared. Table 17-1 shows how the control bits affect the upstream port.
Bit 3 : Bus Activity
This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while writing
a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
Bits 4 and 5 : D– Upstream and D+ Upstream
These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.
Bit 6 : Endpoint Mode
This bit used to configure the number of USB endpoints. See Section 18.2 for a detailed description.
Bit 7 : Endpoint Size
This bit used to configure the number of USB endpoints. See Section 18.2 for a detailed description.
18.0
USB Serial Interface Engine Operation
USB Device Address A includes up to five endpoints: EPA0, EPA1, EPA2, EPA3, and EPA4. Endpoint (EPA0) allows the USB
host to recognize, set-up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up)
packets.
18.1
USB Device Address
The USB Controller provides one USB Device Address with five endpoints. The USB Device Address Register contents are
cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 18-1 shows the
format of the USB Address Registers.
USB Device Address
ADDRESSES 0x10
Bit #
7
6
5
4
3
2
1
0
Bit Name
Endpoint Size
Endpoint Mode
D+ Upstream
D– Upstream
Bus Activity
Control Action
Bit 2
Control Action
Bit 1
Control Action
Bit 0
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 17-1. USB Status and Control Register
Table 17-1. Control Bit Definition for Upstream Port
Control Bits
Control Action
000
Not Forcing (SIE Controls Driver)
001
Force D+[0] HIGH, D–[0] LOW
010
Force D+[0] LOW, D–[0] HIGH
011
Force SE0; D+[0] LOW, D–[0] LOW
100
Force D+[0] LOW, D–[0] LOW
101
Force D+[0] HiZ, D–[0] LOW
110
Force D+[0] LOW, D–[0] HiZ
111
Force D+[0] HiZ, D–[0] HiZ
Bit #
7
6
5
4
3
2
1
0
Bit Name
Device Address
Enable
Device Address
Bit 6
Device Address
Bit 5
Device Address
Bit 4
Device Address
Bit 3
Device Address
Bit 2
Device Address
Bit 1
Device Address
Bit 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 18-1. USB Device Address Registers