Cypress CY7C64013C User Manual

Document #: 38-08001 Rev. *B

Page 36 of 51

Bit 6: Endpoint 0 IN Received 

1= Token received is an IN token. 0= Token received is not an IN token. This bit is set by the SIE to report the type of token

received by the corresponding device address is an IN token. The bit must be cleared by firmware as part of the USB

processing. 

Bit 7: Endpoint 0 SETUP Received 

1= Token received is a SETUP token. 0= Token received is not a SETUP token. This bit is set ONLY by the SIE to report

the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will

clear it (set it to 0). The bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start

of the ACK packet returned by the SIE. The CPU should not clear this bit during this interval, and subsequently, until the

CPU first does an IORD to this endpoint 0 mode register. The bit must be cleared by firmware as part of the USB processing. 

Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits,

which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...

ACK).  The CPU can unlock these bits by doing a subsequent read of this register.  Only endpoint 0 mode registers are locked

when updated.  The locking mechanism does not apply to the mode registers of other endpoints.
Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies

that the contents have changed as desired, and that the SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming

SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 18-1 for the appropriate endpoint zero

memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown inTable 19-1.

Additional information on the mode bits can be found inTable 19-2.

The format of the non-control endpoint mode register is shown in Figure 18-3.

These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in Table

Bit 4 : ACK 

This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.

Must be written zero during register writes. 

 If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the

 mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.

There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers

contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown

in Figure 18-4:

7

6

5

4

3

2

1

0

STALL

Reserved

Reserved

ACK

Mode Bit 3

Mode Bit 2

Mode Bit 1

Mode Bit 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

Data 0/1 Toggle

Data Valid

Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0