Intel cpb4612 User Manual
36
Bit Description
31:20 Reserved
19:0
Preload_Value_2
7.3.3 General Interrupt Status (BAR+08h)
Offset: BAR+08h
Default Value:
00h
Size: 8
bits
Attribute: R/WC
Bit Description
7:1
Reserved
0
Watchdog Timer Interrupt Active
This bit is set when the first stage of the 35 bit down counter reaches zero. This is a sticky bit
and is cleared by writing a ‘1’.
and is cleared by writing a ‘1’.
0 – No Interrupt
1 – Interrupt Active
7.3.4 Reload Register (BAR+0Ch)
Offset: BAR+0Ch
Default Value:
0000h
Size: 16
bits
Attribute: R/W
Bit Description
15:10 Reserved
9
WDT_TIMEOUT
This bit lives in the RTC well and its value is not lost if the host resets the system. It is set to
‘1’ if the host fails to reset the WDT before the down counter reaches 0 during the second
stage. This bit is cleared by performing the register unlocking sequence followed by a ‘1’ to
this bit.
‘1’ if the host fails to reset the WDT before the down counter reaches 0 during the second
stage. This bit is cleared by performing the register unlocking sequence followed by a ‘1’ to
this bit.
8
WDT_RELOAD
To prevent a timeout the host must perform the register unlocking sequence followed by a ‘1’
to this bit.
to this bit.
7:0
Reserved