User ManualTable of ContentsINTRODUCTION1Product Definition2Features4Functional Blocks41.3.1 CompactPCI/PSB Architecture51.3.2 Processor61.3.3 Chipset61.3.4 PCI-to-PCI Bridge61.3.5 Memory and I/O Addressing71.3.6 Power Ramp Circuitry71.3.7 Rear-Panel I/O71.3.8 Video71.3.9 PCI Mezzanine Card (PMC) Interface71.3.10 Dual 10/100/1000 Ethernet Interfaces71.3.11 10/100 Ethernet Interface81.3.12 IDE Hard Drive81.3.13 Serial I/O81.3.14 Interrupts81.3.15 Counter/Timers91.3.16 DMA91.3.17 Real-Time Clock91.3.18 Reset91.3.19 Two-Stage Watchdog Timer91.3.20 Universal Serial Bus (USB)101.3.21 System Environmental Monitor101.3.22 LED Indicators10Software10GETTING STARTED11Unpacking12System Requirements122.2.1 BIOS Version122.2.2 Connectivity122.2.3 Electrical and Environmental12Memory Configuration13I/O Configuration15Connectors16Jumper Options16BIOS Configuration Overview16Operating System Installation17CONFIGURATION19Switch Descriptions213.1.1 PB1 (Reset)213.1.2 J16-1 (BKT-GND to GND)213.1.3 J16-2 (+12V to J5-pin D1)223.1.4 J16-3 (+5V PMC I/O)223.1.5 J16-4 (IMPI Disable)223.1.6 J17-1 (Not Used)223.1.7 J17-2 (CMOS Clear)223.1.8 J17-3 (Disable Onboard Video)233.1.9 J17-4 (Manufacture Test Mode)233.1.10 J18 (Ejector Switch)23RESET24Reset Types and Sources254.1.1 Hard Reset Sources254.1.2 Soft Reset Sources254.1.3 Backend Power Down Sources254.1.4 NMI Sources26SYSTEM MONITORING AND CONTROL27Monitoring and Control Functions28Figure 5.1: Packet Structure28IPMB28Field Replaceable Unit (FRU) Information29Sensors29Firmware Updates29SMBus Address Map29IDE CONTROLLER30Features of the IDE Controller31Disk Drive Support316.2.1 Primary IDE Channel316.2.2 Secondary IDE Channel31IDE I/O Mapping31IDE Device Drivers31WATCHDOG TIMER32Watchdog Timer Overview33PCI Configuration Registers337.2.1 Base Address Register (10h)337.2.2 WDT Configuration Register (60h)347.2.3 WDT Lock Register (68h)34Memory Mapped Registers357.3.1 Preload Value 1 (BAR+00h)357.3.2 Preload Value 2 (BAR+04h)357.3.3 General Interrupt Status (BAR+08h)367.3.4 Reload Register (BAR+0Ch)36Using the Watchdog in an Application377.4.1 WDT Unlocking and Programming Sequence377.4.2 Watchdog Reset377.4.2.1 Load Preload Values377.4.2.2 Enabling the Watchdog Reset377.4.2.3 Reloading the Watchdog37SYSTEM BIOS38BIOS Upgrade and Recovery398.1.1 Flash Utility Program398.1.2 BIOS Recovery39BIOS Configuration Overview398.2.1 Boot Menu408.2.2 ROM Utilities418.2.3 System Summary438.2.4 System Setup448.2.5 IDE Config468.2.6 Hard Disk Setup478.2.7 Boot Order498.2.8 Peripherals518.2.9 USB Configuration538.2.10 MISC Config558.2.11 Event Logging578.2.12 Security/Virus588.2.13 Exit59Plug and Play (PnP)608.3.1 Resource Allocation608.3.2 PnP ISA Auto-configuration608.3.3 PCI Auto-configuration608.3.4 Legacy ISA Configuration618.3.5 Automatic Detection of Video Adapters61Console Redirection61System Management BIOS (SMBIOS)61POST CODE LEDS61SPECIFICATIONS64Electrical and Environmental64Absolute Maximum Ratings64DC Operating Characteristics64Battery Backup Characteristics65Operating Temperature65Reliability65Mechanical65A.4.1 Board Dimensions and Weight66CONNECTORS68Connector Locations69J15 (CompactPCI Bus Connector)71J11 (CompactPCI Bus Connector)72J8 (CompactPCI Connector)73J2 (Rear Panel I/O CompactPCI Connector)74J1 (10/100 Ethernet)75J4 (Universal Serial Bus 0 connector)75J3 (COM1 Serial Port)76J6, J7, J9, J10 (64bit/66Mhz PCI Mezzanine Connectors)76J12 and J13 (32bit/33Mhz PCI Mezzanine Connectors)80J14 (IDE Connector)82THERMAL CONSIDERATIONS84Thermal Requirements85Temperature Monitoring85DATASHEET REFERENCE88CompactPCI89Ethernet89Intel 855GME Chipset89Pentium M processor (FCBGA Package)89PMC Specification90Super I/O90AGENCY APPROVALS92CE Certification92NEBS compliance92Safety92Electro-magnetic Compatibility92Regulatory Information92E.5.1 FCC (USA)92E.5.2 Industry Canada (Canada)93CRT SPECIFICATIONS94Jumper Cross-Reference Table20Connector Assignments68J15 CompactPCI Bus Connector Pin out71J11 CompactPCI Bus Connector Pin out72J8 Connector Pin out73J2 Rear Panel I/O Connector Pin out74J4 Universal Serial Bus 0 Connector Pin out75Thermal Requirements85CPB-4612 Faceplate3Functional Block Diagram5Memory Address Map Example14I/O Address Map15Setup Screen17Default Jumper Configuration21PCB Dimensions66CPB-4612 Connectors Locations (Topside)69Backplane Connectors - Pin Locations70Size: 1.06 MBPages: 104Language: EnglishOpen manual