Intel E7520 User Manual

Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH

Dual-Core Intel

Xeon

processor LV with Intel

E7520 Chipset and Intel

6300ESB ICH

User’s Manual

April 2007

Order Number: 311274-009

3.3.3

Memory Subsystem

The memory subsystem is designed to support Double Data Rate 2 (DDR2)

Synchronous Dynamic Random Access Memory (SDRAM) using the Intel

E7520 MCH.

The MCH provides two independent DDR channels, which support DDR2-400 DIMMs.

The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s)

with DDR2-400. The two DDR2 channels from the MCH operate in lock step; the

effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for

DDR2-400.

3.3.4

Supported DIMM Module Types

Table 4

shows all DIMM technology validated by Intel on the CRB.

3.3.5

Memory Population Rules and Configurations

The system supports four DDR2-400 DIMM slots for Channel A and four DDR2-400

DIMM slots for Channel B. The eight slots are interleaved and placed in a row in the

following order: A1, B1, A2, B2, A3, B3, A4, B4 with A1 being closest to the MCH. This

design supports only registered ECC-enabled DIMMs.

When populating both channels, always place identical DIMMs in sockets that have the

same position on Channel A and Channel B (i.e., DIMM A2 should be identical to DIMM

B2).

In addition, single-rank DIMMs should be populated furthest from the MCH when a

combination of single-rank and double-rank DIMMs are used. This recommendation is

based on the signal integrity requirements of the DDR2 interface.

Table 4.

Supported DIMM Module Types

512M

Size

512M 512M

16G

Channels

Single

Dual

Single

Dual

Note:

SR = Single Rank; DR = Dual Rank