User Manual (AT80604004887AA)Table of Contents1 Introduction91.1 Terminology91.2 References111.3 State of Data112 Electrical Specifications132.1 Processor Maximum Ratings132.2 Socket Voltage Identification142.3 Signal Groups202.4 Processor DC Specifications212.5 Intel® QPI and Intel® SMI Interface Differential Signaling262.5.1 Intel® QPI Signaling Specifications272.5.2 Intel® QPI Electrical Specifications312.5.3 Intel® SMI Signaling Specifications352.5.4 Intel® SMI Transmitter and Receiver Specifications352.6 Platform Environmental Control Interface (PECI) DC Specifications422.6.1 DC Characteristics422.6.2 Input Device Hysteresis422.7 DC Specifications432.8 AC Specifications442.9 Processor AC Timing Waveforms502.10 Flexible Motherboard Guidelines562.11 Reserved (RSVD) or Unused Signals562.12 Test Access Port Connection562.13 Mixing Processors562.14 Processor SPD Interface563 Processor Package Mechanical Specifications573.1 Package Mechanical Specifications573.1.1 Package Mechanical Drawing583.1.2 Processor Component Keep-Out Zones613.1.3 Package Loading Specifications613.1.4 Package Handling Guidelines613.1.5 Package Insertion Specifications613.1.6 Processor Mass Specification623.1.7 Processor Materials623.1.8 Processor Markings623.1.9 Processor Land Coordinates634 Land Listing654.1 Intel® Xeon® Processor 7500 Series Package Bottom Pin Assignments654.1.1 Intel® Xeon® Processor 7500 Series Pin List, Sorted by Land Name654.1.2 Intel® Xeon® Processor 7500 Series Pin List, Sorted by Land Number855 Signal Definitions1056 Thermal Specifications1116.1 Package Thermal Specifications1116.1.1 Thermal Specifications1116.1.2 Thermal Metrology1176.2 Processor Thermal Features1186.2.1 Thermal Monitor Features1186.2.2 Intel® Thermal Monitor 11186.2.3 Intel® Thermal Monitor 21186.2.4 On-Demand Mode1196.2.5 PROCHOT_N Signal1206.2.6 FORCE_PR_N Signal1206.2.7 THERMTRIP_N Signal1216.2.8 THERMALERT_N Signal1216.3 Platform Environment Control Interface (PECI)1216.3.1 PECI Client Capabilities1226.3.2 Client Command Suite1236.3.3 Multi-Domain Commands1396.3.4 Client Responses1396.3.5 Originator Responses1406.3.6 Temperature Data1416.3.7 Client Management1427 Features1457.1 Introduction1457.2 Clock Control and Low Power States1467.2.1 Intel® Xeon® Processor 7500 Series C-State Power Specifications1467.3 Sideband Access to Processor Information ROM via SMBus1467.3.1 Processor Information ROM1467.3.2 Scratch EEPROM1487.3.3 PIROM and Scratch EEPROM Supported SMBus Transactions1497.4 SMBus Memory Component Addressing1497.5 Managing Data in the PIROM1507.5.1 Header1507.5.2 Processor Data1547.5.3 Processor Core Data1567.5.4 Processor Uncore Data1597.5.5 Package Data1647.5.6 Part Number Data1657.5.7 Thermal Reference Data1677.5.8 Feature Data1697.5.9 Other Data1717.5.10 Checksums172Size: 1.66 MBPages: 172Language: EnglishOpen manual
User ManualTable of ContentsDual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH Development Kit1Contents3Figures41 Board before Installing Additional Hardware 1442 Location for the CPU and MCH for Heatsink Installation 1643 CPU Heatsink Top and Bottom View 1744 Processor in Socket and Package Secured 1745 Clean Top of Processor Die 1846 Back Plate in Place 1957 Heatsink Mounted on CPU 1958 Screw Tightening Order 2059 MCH Heatsink Top View 20510 Clean Top of MCH Die 21511 Hook Heatsink Clip to First Anchor 21512 Hook Heatsink Clip to Second Anchor 22513 Block Diagram of Layout 25514 DDR2-400 Memory-DIMM Ordering 29515 ITP location 30516 Power Distribution Block Diagram 31517 Clock Block Diagram 32518 Platform Reset Diagram 33519 SMBus Block Diagram 34520 IRQ Routing Diagram 35521 Evaluation Board 41522 Jumper Locations 52523 Back Panel Connectors 535Tables51 Related Documents 1052 Additional Hardware 1353 Heatsink Information 1554 Supported DIMM Module Types 2855 Processor VRD Settings 3656 Chipset Components 4257 Expansion Slots and Socket 4258 PCI Express* Connector Pinout 4259 32-Bit 5 V PCI Connector Pinout 44510 PCI-X Connector Pinout 45511 On-Board Connector 48512 SATA Connector Pinout 49513 IDE Connector Pinout 49514 Floppy Drive Connector Pinout 50515 Front Panel Connector Pinout 50516 Jumpers and Jumper Functions 51517 SMBUS 3.3 V STBY Pinout 53518 PS/2-Style Mouse and Keyboard Pinout 53519 Parallel Port Connector Pinout 54520 Serial Port Connector Pinout 54521 USB Connector Pinout 54522 Video Port Connector Pinout 55523 Level 1 Debug (Port80/BIOS) 57524 Level 2 Debug (Power Sequence) 57525 Level 3 Debug (Voltage Reference) 5851.0 About This Manual71.1 Content Overview71.2 Text Conventions71.3 Technical Support91.3.1 Electronic Support Systems91.3.2 Online Documents91.3.3 Additional Technical Support91.4 Product Literature101.5 Related Documents102.0 Getting Started112.1 Overview112.2 Evaluation Board Features122.3 Included Hardware122.4 Software Key Features122.4.1 AMIBIOS* for the Development Kit132.5 Before You Begin132.6 Setting up the Evaluation Board132.6.1 Safety142.6.2 Package Contents142.6.3 Installed Hardware152.6.4 Installing the Heatsinks for CPU(s) and MCH152.6.5 CPU Heatsink Installation162.6.6 MCH Heatsink Installation202.6.7 Installing Memory222.6.8 Installing Storage Devices222.6.9 Connect the Video Card and Monitor232.6.10 Connect the Keyboard and Mouse242.6.11 Connect the Power Supply242.6.12 Power up the System242.7 Configuring the BIOS243.0 Theory of Operation253.1 Block Diagram253.2 Thermal Management253.3 System Features263.3.1 Dual-Core Intel® Xeon® processor LV273.3.2 Intel® E7520 MCH and Intel® 6300ESB ICH Chipset273.3.2.1 Intel® E7520 MCH Memory Controller Hub (MCH)273.3.2.2 Intel® 6300ESB I/O Controller Hub (ICH)273.3.3 Memory Subsystem283.3.4 Supported DIMM Module Types283.3.5 Memory Population Rules and Configurations283.3.6 Intel® 82802AC Firmware Hub (FWH)293.3.7 Boot ROM293.3.8 In-Target Probe (ITP)293.3.9 Power Diagram303.3.10 Clock Generation313.3.11 Platform Resets323.3.12 SMBus333.3.13 Platform IRQ Routing343.3.14 VRD VID Headers353.4 Battery Requirements364.0 Platform Management374.1 Power Button374.2 Sleep States Supported374.2.1 S0 State374.2.2 S1 State374.2.3 S2 State374.2.4 S3 State374.2.5 S4 State384.2.6 S5 State384.2.7 Wake-Up Events384.2.8 Wake from S1 Sleep State384.2.9 Wake from S3 State384.2.10 Wake from S5 State394.3 PCI PM Support394.4 Platform Management394.4.1 Processor Thermal Management394.5 System Fan Operation395.0 Driver and OS Support406.0 Hardware Reference416.1 Chipset Components426.2 Expansion Slots and Sockets426.2.1 PCI Express* Connector426.2.2 32-Bit PCI Connector446.2.3 PCI-X Connector456.2.4 Processor Sockets486.2.5 Firmware Hub (FWH) BIOS Socket486.2.6 Battery486.3 On-Board Connectors486.3.1 SATA Connector496.3.2 IDE Connector496.3.3 Floppy Drive Connector506.3.4 Front Panel Connector506.4 Jumpers516.5 SMBUS Headers536.6 Back Panel Connectors536.6.1 PS/2-Style Mouse and Keyboard Connectors536.6.2 Parallel Port536.6.3 Serial Ports546.6.4 Dual Stacked USB Connectors546.6.5 Video Port557.0 Board Setup Checklist568.0 Debug Procedure578.1 Level 1 Debug (Port80/BIOS)578.2 Level 2 Debug (Power Sequence)578.3 Level 3 Debug (Voltage References)58Size: 3.13 MBPages: 58Language: EnglishOpen manual