Intel SA-1100 User Manual
SA-1100 Developer’s Manual
11-93
Peripheral Control Module
11.9.6
SDLC Control Registers 3 and 4
SDLC control register 3 (SDCR3) contains the upper 4 bits and SDLC control register 4 (SDCR4)
the lower 8 bits of the baud rate divisor field.
the lower 8 bits of the baud rate divisor field.
11.9.6.1
Baud Rate Divisor (BRD)
The 12-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the SDLC. A total
of 4096 different baud rates can be selected, ranging from a minimum of 56.24 bps to a maximum
of 230.4 Kbps. The baud rate generator uses the 3.6864-MHz clock generated by the on-chip PLL
and first divides it by the programmable baud rate using BRD. The resultant clock (called the
sample clock) is then divided by 16 to generate the bit clock. The receive baud clock is
synchronized with the data steam each time a transition is detected on the receive data line at a bit’s
boundary. The resultant baud rate given a specific BRD value, or required BRD value given a
desired baud rate, can be calculated using the following two respective equations, where BRD is
the decimal equivalent of the unsigned binary value programmed within the bit field:
of 4096 different baud rates can be selected, ranging from a minimum of 56.24 bps to a maximum
of 230.4 Kbps. The baud rate generator uses the 3.6864-MHz clock generated by the on-chip PLL
and first divides it by the programmable baud rate using BRD. The resultant clock (called the
sample clock) is then divided by 16 to generate the bit clock. The receive baud clock is
synchronized with the data steam each time a transition is detected on the receive data line at a bit’s
boundary. The resultant baud rate given a specific BRD value, or required BRD value given a
desired baud rate, can be calculated using the following two respective equations, where BRD is
the decimal equivalent of the unsigned binary value programmed within the bit field:
The following tables show the bit locations corresponding to the baud rate divisor field that is split
between two 8-bit registers. The upper 4 bits of BRD reside within SDCR3 and the lower 8 bits
reside within SDCR4. The SDLC must be disabled (SUS=RXE=TXE=0) whenever these registers
are written. Note that writes to reserved bits are ignored and reads return zeros; question marks
indicate that the values are unknown at reset.
between two 8-bit registers. The upper 4 bits of BRD reside within SDCR3 and the lower 8 bits
reside within SDCR4. The SDLC must be disabled (SUS=RXE=TXE=0) whenever these registers
are written. Note that writes to reserved bits are ignored and reads return zeros; question marks
indicate that the values are unknown at reset.
BaudRa te
3.6864
6
×
10
16
x
BR D
1
+
(
)
---------------------------------------
=
BRD
3.6864
6
×
10
16
x
Bau dRate
-----------------------------------------
1
–
=
Address: 0h 8002 006C
SDCR3
Read/Write
Bit
7
6
5
4
3
2
1
0
Reserved
BRD<11:8>
Reset
0
0
0
0
?
?
?
?
Bit
Name
Description
3..0
BRD<11:8
>
>
Baud rate divisor.
Encoded value (from 0 to 4096). Used to generate the baud rate of the SDLC.
Baud Rate = 3.6864x10
6
/(16x(BRD+1)), where BRD is a decimal value.
7..4
—
Reserved.
Address: 0h 8002 0070
SDCR4
Read/Write
Bit
7
6
5
4
3
2
1
0
BRD<7:0>
Reset
?
?
?
?
?
?
?
?
Bit
Name
Description
7..0
BRD<7:0>
Baud rate divisor.
Encoded value (from 0 to 4096). Used to generate the baud rate of the SDLC.
Baud Rate = 3.6864x10
6
/(16x(BRD+1)), where BRD is a decimal value.