User ManualTable of ContentsIntel® StrongARM® SA-1100 Microprocessor Developer's Manual1Copyright Page2Contents3Figures17Tables18Introduction 1211.1 Intel® StrongARM® SA-1100 Microprocessor211.2 Overview241.3 Example System251.4 ARM™ Architecture261.4.1 26-Bit Mode261.4.2 Coprocessors261.4.3 Memory Management261.4.4 Instruction Cache261.4.5 Data Cache261.4.6 Write Buffer271.4.7 Read Buffer27Functional Description 2292.1 Block Diagram292.2 Inputs/Outputs312.3 Signal Description322.4 Memory Map35ARM™ Implementation Options 3373.1 Big and Little Endian373.2 Exceptions373.2.1 Power-Up Reset383.2.2 ROM Size Select383.2.3 Abort393.2.4 Vector Summary403.2.5 Exception Priorities403.2.6 Interrupt Latencies and Enable Timing413.3 Coprocessors41Instruction Set 4434.1 Instruction Set434.2 Instruction Timings43Coprocessors 5455.1 Internal Coprocessor Instructions455.2 Coprocessor 15 Definition465.2.1 Register 0 – ID465.2.2 Register 1 – Control475.2.3 Register 2 – Translation Table Base485.2.4 Register 3 – Domain Access Control485.2.5 Register 4 – RESERVED485.2.6 Register 5 – Fault Status485.2.7 Register 6 – Fault Address485.2.8 Register 7 – Cache Control Operations495.2.9 Register 8 – TLB Operations495.2.10 Register 9 – Read-Buffer Operations505.2.11 Registers 10 – 12 RESERVED505.2.12 Register 13 – Process ID Virtual Address Mapping515.2.13 Register 14 – Debug Support (Breakpoints)525.2.14 Register 15 – Test, Clock, and Idle Control53Caches, Write Buffer, and Read Buffer 6556.1 Instruction Cache (Icache)556.1.1 Icache Operation556.1.2 Icache Validity556.1.2.1 Software Icache Flush556.1.3 Icache Enable/Disable and Reset566.1.3.1 Enabling the Icache566.1.3.2 Disabling the Icache566.2 Data Caches (Dcaches)566.2.1 Cacheable Bit – C576.2.1.1 Cacheable Reads – C = 1576.2.1.2 Noncacheable Reads – C = 0576.2.2 Bufferable Bit – B576.2.3 Software Dcache Flush586.2.3.1 Doubly Mapped Space586.2.4 Dcaches Enable/Disable and Reset586.2.4.1 Enabling the Dcaches596.2.4.2 Disabling the Dcaches596.3 Write Buffer (WB)596.3.1 Bufferable Bit596.3.2 Write Buffer Operation596.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1)596.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0)606.3.2.3 Unbufferable Writes (B=0)606.3.3 Enabling the Write Buffer606.3.3.1 Disabling the Write Buffer606.4 Read Buffer (RB)60Memory-Management Unit (MMU) 7637.1 Overview637.1.1 MMU Registers637.2 MMU Faults and CPU Aborts637.3 Data Aborts637.3.1 Cacheable Reads (Linefetches)647.3.2 Buffered Writes647.4 Interaction of the MMU, Icache, Dcache, and Write Buffer647.5 Mini Data Cache65Clocks 8678.1 SA-1100 Crystal Oscillators678.2 Core Clock Configuration Register688.2.1 Restrictions on Changing the Core Clock Configuration688.3 Driving SA-1100 Crystal Pins from an External Source698.4 Clocking During Test70System Control Module 9719.1 General-Purpose I/O719.1.1 GPIO Register Definitions729.1.1.1 GPIO Pin-Level Register (GPLR)739.1.1.2 GPIO Pin Direction Register (GPDR)749.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output Clear Register (GPCR)759.1.1.4 GPIO Rising-Edge Detect Register (GRER) and Falling-Edge Detect Register (GFER)769.1.1.5 GPIO Edge Detect Status Register (GEDR)779.1.1.6 GPIO Alternate Function Register (GAFR)789.1.2 GPIO Alternate Functions799.1.3 GPIO Register Locations809.2 Interrupt Controller819.2.1 Interrupt Controller Register Definitions819.2.1.1 Interrupt Controller Pending Register (ICPR)829.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)839.2.1.3 Interrupt Controller Mask Register (ICMR)849.2.1.4 Interrupt Controller Level Register (ICLR)859.2.1.5 Interrupt Controller Control Register (ICCR)869.2.2 Interrupt Controller Register Locations879.3 Real-Time Clock879.3.1 RTC Counter Register (RCNR)879.3.2 RTC Alarm Register (RTAR)889.3.3 RTC Status Register (RTSR)889.3.4 RTC Trim Register (RTTR)899.3.5 Trim Procedure899.3.5.1 Oscillator Frequency Calibration899.3.5.2 RTTR Value Calculations909.3.6 Real-Time Clock Register Locations919.4 Operating System Timer919.4.1 OS Timer Count Register (OSCR)929.4.2 OS Timer Match Registers 0–3 (OSMR<0>, OSMR<1>, OSMR<2>, OSMR<3>)929.4.3 OS Timer Watchdog Match Enable Register (OWER)929.4.4 OS Timer Status Register (OSSR)939.4.5 OS Timer Interrupt Enable Register (OIER)949.4.6 Watchdog Timer949.4.7 OS Timer Register Locations959.5 Power Manager969.5.1 Run Mode969.5.2 Idle Mode969.5.2.1 Entering Idle Mode969.5.2.2 Exiting Idle Mode979.5.3 Sleep Mode979.5.3.1 CPU Preparation for Sleep Mode979.5.3.2 Events Causing Entry into Sleep Mode979.5.3.3 The Sleep Shutdown Sequence989.5.3.4 During Sleep Mode989.5.3.5 The Sleep Wake-Up Sequence989.5.3.6 Booting After Sleep Mode999.5.3.7 Reviving the DRAMs from Self-Refresh Mode1009.5.4 Notes on Power Supply Sequencing1009.5.5 Assumed Behavior of an SA-1100 System in Sleep Mode1009.5.6 Pin Operation in Sleep Mode1029.5.7 Power Manager Registers1039.5.7.1 Power Manager Control Register (PMCR)1039.5.7.2 Power Manager General Configuration Register (PCFR)1049.5.7.3 Power Manager PLL Configuration Register (PPCR)1059.5.7.4 Power Manager Wake-Up Enable Register (PWER)1069.5.7.5 Power Manager Sleep Status Register (PSSR)1079.5.7.6 Power Manager Scratch Pad Register (PSPR)1099.5.7.7 Power Manager GPIO Sleep State Register (PGSR)1099.5.7.8 Power Manager Oscillator Status Register (POSR)1109.5.8 Power Manager Register Locations1109.6 Reset Controller1119.6.1 Reset Controller Registers1129.6.1.1 Reset Controller Software Reset Register (RSRR)1129.6.1.2 Reset Controller Status Register (RCSR)1139.6.2 Reset Controller Register Locations113Memory and PCMCIA Control Module 1011510.1 Overview of Operation11510.1.1 Example Memory System11710.1.2 Types of Memory Accesses11810.1.3 Reads11810.1.4 Writes11810.1.5 Transaction Summary11810.1.6 Read-Lock-Write11910.1.7 Aborts and Nonexistent Memory11910.2 Memory Configuration Registers12010.2.1 DRAM Configuration Register (MDCNFG)12110.2.2 DRAM CAS Waveform Shift Registers (MDCAS0, MDCAS1, MDCAS2)12310.2.3 Static Memory Control Registers (MSC1–0)12410.2.4 Expansion Memory (PCMCIA) Configuration Register (MECR)12610.3 Dynamic Interface Operation12810.3.1 DRAM Overview12810.3.2 DRAM Timing12910.3.3 DRAM Refresh13210.3.4 DRAM Self-Refresh in Sleep Mode13210.4 Static Memory Interface13210.4.1 ROM Interface Overview13310.4.2 ROM Timing Diagrams and Parameters13310.4.3 SRAM Interface Overview13610.4.4 SRAM Timing Diagrams and Parameters13610.4.5 FLASH EPROM Interface Overview13710.4.6 FLASH EPROM Timing Diagrams and Parameters13810.5 General Memory BUS Timing13910.5.1 Static Access Followed by a DRAM Access13910.5.2 DRAM Access Followed by a Static Access13910.5.3 DRAM Access Followed by a Refresh Operation13910.6 PCMCIA Overview14010.6.1 32-Bit Data Bus Operation14110.6.2 External Logic for PCMCIA Implementation14210.6.3 PCMCIA Interface Timing Diagrams and Parameters14510.7 Initialization of the Memory Interface14810.7.1 Flow of Events After Reset or Exiting Sleep Mode14810.8 Alternate Memory Bus Master Mode149Peripheral Control Module 1115111.1 Read/Write Interface15111.2 Memory Organization15211.3 Interrupts15411.4 Peripheral Pins15511.5 Use of the GPIO Pins for Alternate Functions15611.6 DMA Controller15711.6.1 DMA Register Definitions15711.6.1.1 DMA Device Address Register (DDARn)15811.6.1.2 DMA Control/Status Register (DCSRn)16111.6.1.3 DMA Buffer A Start Address Register (DBSAn)16211.6.1.4 DMA Buffer A Transfer Count Register (DBTAn)16211.6.1.5 DMA Buffer B Start Address Register (DBSBn)16311.6.1.6 DMA Buffer B Transfer Count Register (DBTBn)16311.6.2 DMA Operation16311.6.3 DMA Register List16411.7 LCD Controller16611.7.1 LCD Controller Operation16811.7.1.1 DMA to Memory Interface16811.7.1.2 Frame Buffer16811.7.1.3 Input FIFO17311.7.1.4 Lookup Palette17311.7.1.5 Color/Gray-Scale Dithering17411.7.1.6 Output FIFO17411.7.1.7 LCD Controller Pins17511.7.2 LCD Controller Register Definitions17511.7.3 LCD Controller Control Register 017611.7.3.1 LCD Enable (LEN)17611.7.3.2 Color/Monochrome Select (CMS)17611.7.3.3 Single-/Dual-Panel Select (SDS)17611.7.3.4 LCD Disable Done Interrupt Mask (LDM)17911.7.3.5 Base Address Update Interrupt Mask (BAM)17911.7.3.6 Error Interrupt Mask (ERM)17911.7.3.7 Passive/Active Display Select (PAS)17911.7.3.8 Big/Little Endian Select (BLE)18111.7.3.9 Double-Pixel Data (DPD) Pin Mode18111.7.3.10 Palette DMA Request Delay (PDD)18111.7.4 LCD Controller Control Register 118411.7.4.1 Pixels Per Line (PPL)18411.7.4.2 Horizontal Sync Pulse Width (HSW)18411.7.4.3 End-of-Line Pixel Clock Wait Count (ELW)18411.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW)18511.7.5 LCD Controller Control Register 218611.7.5.1 Lines Per Panel (LPP)18611.7.5.2 Vertical Sync Pulse Width (VSW)18611.7.5.3 End-of-Frame Line Clock Wait Count (EFW)18711.7.5.4 Beginning-of-Frame Line Clock Wait Count (BFW)18711.7.6 LCD Controller Control Register 318911.7.6.1 Pixel Clock Divider (PCD)18911.7.6.2 AC Bias Pin Frequency (ACB)18911.7.6.3 AC Bias Pin Transitions Per Interrupt (API)19011.7.6.4 Vertical Sync Polarity (VSP)19011.7.6.5 Horizontal Sync Polarity (HSP)19011.7.6.6 Pixel Clock Polarity (PCP)19011.7.6.7 Output Enable Polarity (OEP)19111.7.7 LCD Controller DMA Registers19211.7.8 DMA Channel 1 Base Address Register19311.7.9 DMA Channel 1 Current Address Register19411.7.10 DMA Channel 2 Base and Current Address Registers19511.7.11 LCD Controller Status Register19611.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt)19611.7.11.2 Base Address Update Flag (BAU) (read-only, maskable interrupt)19611.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt)19611.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt)19711.7.11.5 Input FIFO Overrun Lower Panel Status (IOL) (read/write, maskable interrupt)19711.7.11.6 Input FIFO Underrun Lower Panel Status (IUL) (read/write, maskable interrupt)19711.7.11.7 Input FIFO Overrun Upper Panel Status (IOU) (read/write, maskable interrupt)19711.7.11.8 Input FIFO Underrun Upper Panel Status (IUU) (read/write, maskable interrupt)19711.7.11.9 Output FIFO Overrun Lower Panel Status (OOL) (read/write, maskable interrupt)19711.7.11.10 Output FIFO Underrun Lower Panel Status (OUL) (read/write, maskable interrupt)19811.7.11.11 Output FIFO Overrun Upper Panel Status (OOU) (read/write, maskable interrupt)19811.7.11.12 Output FIFO Underrun Upper Panel Status (OUU) (read/write, maskable interrupt)19811.7.12 LCD Controller Register Locations20011.7.13 LCD Controller Pin Timing Diagrams20111.8 Serial Port 0 – USB Device Controller20611.8.1 USB Operation20611.8.1.1 Signalling Levels20711.8.1.2 Bit Encoding20811.8.1.3 Field Formats20911.8.1.4 Packet Formats21011.8.1.5 Transaction Formats21111.8.1.6 UDC Device Requests21211.8.2 UDC Register Definitions21311.8.3 UDC Control Register21411.8.3.1 UDC Disable (UDD)21411.8.3.2 UDC Active (UDA)21411.8.3.3 Bit 2 Reserved21411.8.3.4 Endpoint 0 Interrupt Mask (EIM)21411.8.3.5 Receive Interrupt Mask (RIM)21411.8.3.6 Transmit Interrupt Mask (TIM)21411.8.3.7 Suspend/Resume Interrupt Mask (SRM)21511.8.3.8 Reset Interrupt Mask (REM)21511.8.4 UDC Address Register21611.8.5 UDC OUT Max Packet Register21611.8.6 UDC IN Max Packet Register21711.8.7 UDC Endpoint 0 Control/Status Register21811.8.7.1 OUT Packet Ready (OPR)21811.8.7.2 IN Packet Ready (IPR)21811.8.7.3 Sent Stall (SST)21811.8.7.4 Force Stall (FST)21811.8.7.5 Data End (DE)21811.8.7.6 Setup End (SE)21811.8.7.7 Serviced OPR (SO)21811.8.7.8 Serviced Setup End (SSE)21911.8.8 UDC Endpoint 1 Control/Status Register22011.8.8.1 Receive FIFO Service (RFS)22011.8.8.2 Receive Packet Complete (RPC)22011.8.8.3 Receive Packet Error (RPE)22011.8.8.4 Sent Stall (SST)22011.8.8.5 Force Stall (FST)22011.8.8.6 Receive FIFO Not Empty (RNE)22011.8.8.7 Bits 7..6 Reserved22111.8.9 UDC Endpoint 2 Control/Status Register22211.8.9.1 Transmit FIFO Service (TFS)22211.8.9.2 Transmit Packet Complete (TPC)22211.8.9.3 Transmit Packet Error (TPE)22211.8.9.4 Transmit Underrun (TUR)22211.8.9.5 Sent STALL (SST)22211.8.9.6 Force STALL (FST)22211.8.9.7 Bits 7..6 Reserved22311.8.10 UDC Endpoint 0 Data Register22411.8.11 UDC Endpoint 0 Write Count Register22411.8.12 UDC Data Register22511.8.13 UDC Status/Interrupt Register22611.8.13.1 Endpoint 0 Interrupt Request (EIR)22611.8.13.2 Receive Interrupt Request (RIR)22611.8.13.3 Transmit Interrupt Request (TIR)22611.8.13.4 Suspend Interrupt Request (SUSIR)22611.8.13.5 Resume Interrupt Request (RESIR)22611.8.13.6 Reset Interrupt Request (RSTIR)22711.8.14 UDC Register Locations22811.9 Serial Port 1 – SDLC/UART22811.9.1 SDLC Operation22911.9.1.1 Bit Encoding22911.9.1.2 Frame Format23011.9.1.3 Address Field23011.9.1.4 Control Field23011.9.1.5 Data Field23111.9.1.6 CRC Field23111.9.1.7 Baud Rate Generation23111.9.1.8 Receive Operation23211.9.1.9 Transmit Operation23311.9.1.10 Simultaneous Use of the UART and SDLC23311.9.1.11 Transmit and Receive FIFOs23411.9.1.12 CPU and DMA Register Access Sizes23411.9.2 SDLC Register Definitions23411.9.3 SDLC Control Register 023511.9.3.1 SDLC/UART Select (SUS)23511.9.3.2 Single/Double Flag Select (SDF)23511.9.3.3 Loopback Mode (LBM)23511.9.3.4 Bit Modulation Select (BMS)23611.9.3.5 Sample Clock Enable (SCE)23611.9.3.6 Sample Clock Direction (SCD)23611.9.3.7 Receive Clock Edge Select (RCE)23711.9.3.8 Transmit Clock Edge Select (TCE)23711.9.4 SDLC Control Register 123811.9.4.1 Abort After Frame (AAF)23811.9.4.2 Transmit Enable (TXE)23911.9.4.3 Receive Enable (RXE)23911.9.4.4 Receive FIFO Interrupt Enable (RIE)23911.9.4.5 Transmit FIFO Interrupt Enable (TIE)23911.9.4.6 Address Match Enable (AME)24011.9.4.7 Transmit FIFO Underrun Select (TUS)24011.9.4.8 Receiver Abort Interrupt Enable(RAE)24011.9.5 SDLC Control Register 224211.9.5.1 Address Match Value (AMV)24211.9.6 SDLC Control Registers 3 and 424311.9.6.1 Baud Rate Divisor (BRD)24311.9.7 SDLC Data Register24411.9.8 SDLC Status Register 024611.9.8.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)24611.9.8.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)24611.9.8.3 Receiver Abort Status (RAB) (read/write, maskable interrupt)24611.9.8.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)24711.9.8.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)24711.9.9 SDLC Status Register 124911.9.9.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)24911.9.9.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)24911.9.9.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)24911.9.9.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)24911.9.9.5 Receive Transition Detect Status (RTD) (read/write, noninterruptible)24911.9.9.6 End of Frame Flag (EOF) (read-only, noninterruptible)24911.9.9.7 CRC Error Status (CRE) (read-only, noninterruptible)25011.9.9.8 Receiver Overrun Status (ROR) (read-only, noninterruptible)25011.9.10 UART Register Locations25211.9.11 SDLC Register Locations25311.10 Serial Port 2 – Infrared Communications Port (ICP)25311.10.1 Low-Speed ICP Operation25411.10.1.1 HP-SIR* Modulation25411.10.1.2 UART Frame Format25411.10.2 High-Speed ICP Operation25511.10.2.1 4PPM Modulation25511.10.2.2 HSSP Frame Format25611.10.2.3 Address Field25711.10.2.4 Control Field25711.10.2.5 Data Field25711.10.2.6 CRC Field25711.10.2.7 Baud Rate Generation25811.10.2.8 Receive Operation25811.10.2.9 Transmit Operation25911.10.2.10 Transmit and Receive FIFOs26011.10.2.11 CPU and DMA Register Access Sizes26011.10.3 UART Register Definition26111.10.4 UART Control Register 426111.10.4.1 HP-SIR Enable (HSE)26111.10.4.2 Low-Power Mode (LPM)26111.10.5 HSSP Register Definitions26211.10.6 HSSP Control Register 026211.10.6.1 IrDA Transmission Rate (ITR)26211.10.6.2 Loopback Mode (LBM)26211.10.6.3 Transmit FIFO Underrun Select (TUS)26311.10.6.4 Transmit Enable (TXE)26311.10.6.5 Receive Enable (RXE)26411.10.6.6 Receive FIFO Interrupt Enable (RIE)26411.10.6.7 Transmit FIFO Interrupt Enable (TIE)26411.10.6.8 Address Match Enable (AME)26411.10.7 HSSP Control Register 126611.10.7.1 Address Match Value (AMV)26611.10.8 HSSP Control Register 226711.10.8.1 Transmit Pin Polarity Select (TXP)26711.10.8.2 Receive Pin Polarity Select (RXP)26711.10.9 HSSP Data Register26911.10.10 HSSP Status Register 027111.10.10.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)27111.10.10.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)27111.10.10.3 Receiver Abort Status (RAB) (read/write, nonmaskable interrupt)27111.10.10.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)27211.10.10.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)27211.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt)27311.10.11 HSSP Status Register 127411.10.11.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)27411.10.11.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)27411.10.11.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)27411.10.11.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)27411.10.11.5 End-of-Frame Flag (EOF) (read-only, noninterruptible)27411.10.11.6 CRC Error Status (CRE) (read-only, noninterruptible)27511.10.11.7 Receiver Overrun Status (ROR) (read-only, noninterruptible)27511.10.12 UART Register Locations27711.10.13 HSSP Register Locations27711.11 Serial Port 3 - UART27811.11.1 UART Operation27811.11.1.1 Frame Format27911.11.1.2 Baud Rate Generation27911.11.1.3 Receive Operation27911.11.1.4 Transmit Operation28011.11.1.5 Transmit and Receive FIFOs28011.11.1.6 CPU and DMA Register Access Sizes28111.11.2 UART Register Definitions28111.11.3 UART Control Register 028111.11.3.1 Parity Enable (PE)28111.11.3.2 Odd/Even Parity Select (OES)28111.11.3.3 Stop Bit Select (SBS)28211.11.3.4 Data Size Select (DSS)28211.11.3.5 Sample Clock Enable (SCE)28211.11.3.6 Receive Clock Edge Select (RCE)28211.11.3.7 Transmit Clock Edge Select (TCE)28311.11.4 UART Control Registers 1 and 228411.11.4.1 Baud Rate Divisor (BRD)28411.11.5 UART Control Register 328511.11.5.1 Receiver Enable (RXE)28511.11.5.2 Transmitter Enable (TXE)28511.11.5.3 Break (BRK)28511.11.5.4 Receive FIFO Interrupt Enable (RIE)28511.11.5.5 Transmit FIFO Interrupt Enable (TIE)28611.11.5.6 Loopback Mode (LBM)28611.11.6 UART Data Register28711.11.7 UART Status Register 028911.11.7.1 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)28911.11.7.2 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)28911.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt)29011.11.7.4 Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt)29011.11.7.5 Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)29011.11.7.6 Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt)29011.11.8 UART Status Register 129211.11.8.1 Transmitter Busy Flag (TBY) (read-only, noninterruptible)29211.11.8.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)29211.11.8.3 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)29211.11.8.4 Parity Error Flag (PRE) (read-only, noninterruptible)29211.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible)29311.11.8.6 Receiver Overrun Flag (ROR) (read-only, noninterruptible)29311.11.9 UART Register Locations29511.12 Serial Port 4 – MCP / SSP29511.12.1 MCP Operation29611.12.1.1 Frame Format29711.12.1.2 Audio and Telecom Sample Rates and Data Transfer29811.12.1.3 MCP Transmit and Receive FIFO Operation29911.12.1.4 Codec Control Register Data Transfer30011.12.1.5 External Clock Operation30111.12.1.6 Alternate SSP Pin Assignment30111.12.1.7 CPU and DMA Register Access Sizes30111.12.2 MCP Register Definitions30211.12.3 MCP Control Register30211.12.3.1 Audio Sample Rate Divisor (ASD)30211.12.3.2 Telecom Sample Rate Divisor (TSD)30311.12.3.3 Multimedia Communications Port Enable (MCE)30411.12.3.4 External Clock Select (ECS)30411.12.3.5 A/D Sampling Mode (ADM)30411.12.3.6 Telecom Transmit FIFO Interrupt Enable (TTE)30511.12.3.7 Telecom Receive FIFO Interrupt Enable (TRE)30511.12.3.8 Audio Transmit FIFO Interrupt Enable (ATE)30511.12.3.9 Audio Receive FIFO Interrupt Enable (ARE)30511.12.3.10 Loopback Mode (LBM)30611.12.3.11 External Clock Prescaler (ECP)30611.12.4 MCP Control Register 130811.12.4.1 Clock Frequency Select (CFS)30811.12.5 MCP Data Registers30811.12.5.1 MCP Data Register 030911.12.5.2 MCP Data Register 131011.12.5.3 MCP Data Register 231111.12.6 MCP Status Register31311.12.6.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)31311.12.6.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt)31311.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt)31411.12.6.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrupt)31411.12.6.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, nonmaskable interrupt)31411.12.6.6 Audio Receive FIFO Overrun Status (ARO) (read/write, nonmaskable interrupt)31411.12.6.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, nonmaskable interrupt)31511.12.6.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, nonmaskable interrupt)31511.12.6.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, noninterruptible)31511.12.6.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, noninterruptible)31511.12.6.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)31511.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, noninterruptible)31611.12.6.13 Codec Write Completed Flag (CWC) (read-only, noninterruptible)31611.12.6.14 Codec Read Completed Flag (CRC) (read-only, noninterruptible)31611.12.6.15 Audio Codec Enabled Flag (ACE) (read-only, noninterruptible)31611.12.6.16 Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible)31611.12.7 SSP Operation31911.12.7.1 Frame Format31911.12.7.2 Baud Rate Generation32311.12.7.3 SSP Transmit and Receive FIFOs32311.12.7.4 CPU and DMA Register Access Sizes32411.12.7.5 Alternate SSP Pin Assignment32411.12.8 SSP Register Definitions32411.12.9 SSP Control Register 032411.12.9.1 Data Size Select (DSS)32511.12.9.2 Frame Format (FRF)32511.12.9.3 Synchronous Serial Port Enable (SSE)32511.12.9.4 Serial Clock Rate (SCR)32611.12.10 SSP Control Register 132711.12.10.1 Receive FIFO Interrupt Enable (RIE)32711.12.10.2 Transmit FIFO Interrupt Enable (TIE)32711.12.10.3 Loopback Mode (LBM)32711.12.10.4 Serial Clock Polarity (SPO)32711.12.10.5 Serial Clock Phase (SPH)32811.12.10.6 External Clock Select (ECS)32911.12.11 SSP Data Register33011.12.12 SSP Status Register33111.12.12.1 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)33111.12.12.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)33111.12.12.3 SSP Busy Flag (BSY) (read-only, noninterruptible)33111.12.12.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)33111.12.12.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)33211.12.12.6 Receiver Overrun Status (ROR) (read/write, nonmaskable interrupt)33211.12.13 MCP Register Locations33311.12.14 SSP Register Locations33311.13 Peripheral Pin Controller (PPC)33411.13.1 PPC Operation33411.13.2 PPC Register Definitions33511.13.3 PPC Pin Direction Register33511.13.4 PPC Pin State Register33711.13.5 PPC Pin Assignment Register33911.13.5.1 UART Pin Reassignment (UPR)33911.13.5.2 SSP Pin Reassignment (SPR)33911.13.6 PPC Sleep Mode Pin Direction Register34011.13.7 PPC Pin Flag Register34211.13.8 PPC Register Locations343DC Parameters 1234512.1 Absolute Maximum Ratings34512.2 DC Operating Conditions34612.3 Power Supply Voltages and Currents347AC Parameters 1334913.1 Test Conditions34913.2 Module Considerations35013.3 Memory Bus and PCMCIA Signal Timings35013.4 LCD Controller Signals35113.5 MCP Signals35113.6 Timing Parameters35213.6.1 Asynchronous Signal Timing Descriptions353Package and Pinout 1435514.1 Mechanical Data and Packaging Information35514.2 Mini-Ball Grid Array – (mBGA)357Debug Support 1535915.1 Instruction Breakpoint35915.2 Data Breakpoint359Boundary-Scan Test Interface 1636116.1 Overview36116.2 Reset36216.3 Pull-Up Resistors36216.4 Instruction Register36216.5 Public Instructions36216.5.1 EXTEST (00000)36316.5.2 SAMPLE/PRELOAD (00001)36316.5.3 CLAMP (00100)36316.5.4 HIGHZ (00101)36416.5.5 IDCODE (00110)36416.5.6 BYPASS (11111)36416.6 Test Data Registers36516.6.1 Bypass Register36516.6.2 SA-1100 Device Identification (ID) Code Register36616.6.3 SA-1100 Boundary-Scan (BS) Register36616.7 Boundary-Scan Interface Signals367Register Summary A3713.6864–MHz Oscillator Specifications B377B.1 Specifications377B.1.1 System Specifications377B.1.1.1. Parasitic Capacitance Off-chip Between PXTAL and PEXTAL378B.1.1.2. Parasitic Capacitance Off-chip Between PXTAL or PEXTAL and VSS378B.1.1.3. Parasitic Resistance Between PXTAL and PEXTAL378B.1.1.4. Parasitic Resistance Between PXTAL or PEXTAL and VSS378B.1.2 Quartz Crystal Specification37932.768–kHz Oscillator Specifications C381C.1 Specifications381C.1.1 System Specifications381C.1.1.1. Temperature Range381C.1.1.2. Current Consumption381C.1.1.3. Startup Time381C.1.1.4. Frequency Shift Due to Temperature Effect on the Circuit382C.1.1.5. Parasitic Capacitance Off-chip Between TXTAL and TEXTAL382C.1.1.6. Parasitic Capacitance Off-chip Between TXTAL or TEXTAL and VSS382C.1.1.7. Parasitic Resistance Between TXTAL and TEXTAL382C.1.1.8. Parasitic Resistance Between TXTAL or TEXTAL and VSS382C.1.2 Quartz Crystal Specification383Internal Test D385D.1 Test Unit Control Register (TUCR)385Support, Products, and Documentation388Size: 4.6 MBPages: 388Language: EnglishOpen manual