Fujitsu FR81S User Manual
CHAPTER 30: POWER CONSUMPTION CONTROL
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : POWER CONSUMPTION CONTROL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
52
5.9. Transition to Illegal Standby Mode
Transition to illegal standby mode is described below.
If the transition from PLL run state to standby mode (watch mode/watch mode (power-shutdown)/stop
mode/stop mode (power-shutdown)) is made, standby mode is set and PLL oscillation stabilization is
canceled. (Transition to illegal standby mode)
After returning from standby mode, CSELR.CKS[1:0]=00 and CMONR.CKM[1:0]=00 (divide-by-two
output of the main clock).
The PSTF flag of the CPUAR register is set concurrently with the transition to standby mode. When the
PSTRE bit in the CPUAR register is set, reset occurs by illegal standby mode transition detection reset
source. For the CPUAR register, see " CPU Abnormal Operation Register: CPUAR (CPU Abnormal
operation Register)
" in "CHAPTER: RESET".
Figure 5-5 Generation Diagram of Illegal Standby Mode Transition Detection Reset Source
CPUAR.
PSTF
CPUAR.
PSTRE
set
PLL/SSCG clock is being
selected as a clock source.
selected as a clock source.
Generation of transition to
Watch mode/Stop mode
Watch mode/Stop mode
Illegal standby mode
transition detection reset
factor
MB91520 Series
MN705-00010-1v0-E
1139