Fujitsu FR81S User Manual
CHAPTER 37: BUS PERFORMANCE COUNTERS
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BUS PERFORMANCE COUNTERS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Features
This section explains the features of the bus performance counters.
Counter configuration
Count clocks :
Clock for the on-chip bus
Counter bit length :
32-bit × 3 channels (BPC-A, BPC-B, BPC-C)
Overflow detection :
None
Counter value rewrite : Allowed
Main functions
The following operations can be selected for counting in each channel
⋅
Number of read accesses in the on-chip bus
⋅
Number of write accesses in the on-chip bus
⋅
Number of wait cycles in the on-chip bus
One of the following operations can be selected for counting in each channel
⋅
Specific bus master (CPU, DMAC, other, or all)
⋅
Specific target (ICH, MCH, other, or all)
MB91520 Series
MN705-00010-1v0-E
1253