Fujitsu FR81S User Manual
CHAPTER 37: BUS PERFORMANCE COUNTERS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BUS PERFORMANCE COUNTERS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. BPC-A Control Register : BPCCRA (Bus Performance
Counter Control Register A)
The bit configuration of the BPC-A control register is shown below.
This register configures the measurement target of bus performance counter A (BPC-A).
The bus performance counters have three channels, A, B, and C, and there is a control register for each of
these counters. Each field of the control register is common to each channel.
BPCCRA : Address 0710
H
(Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FUNC[1:0]
MST[3:0]
SLV[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] FUNC[1:0] (Function Selection) : Measurement event selection
These bits select the event measured by BPC.
FUNC[1:0]
Event
00
BPC-A operation stopped (initial value)
01
Number of read accesses
10
Number of write accesses
11
Number of wait cycles
[bit5 to bit2] MST[3:0] (bus MaSTer select) : Bus master selection
These bits select the bus master for the events which are measured by BPC.
MST[3:0]
Bus master
0000
All bus masters (initial value)
0001
CPU (XBS)
0010
DMAC
0011
Reserved
0100
Reserved
Except for the
above
Reserved
MB91520 Series
MN705-00010-1v0-E
1256