Fujitsu FR81S User Manual
CHAPTER 37: BUS PERFORMANCE COUNTERS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BUS PERFORMANCE COUNTERS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
5.1. Setting
This section explains the setting.
Before starting each of the BPC channels, write "0x00000000" to BPCTRA, BPCTRB, and BPCTRC, and
initialize each counter. Initialize each counter in the same way when changing the measurement target.
Because the counter value is undefined after reset, always write the counter value before enabling operation.
When starting each BPC channel, configure the measurement target of each counter using BPCCRA,
BPCCRB, and BPCCRC.
The events monitored by the settings of the bus performance counter A (B, C) control register (BPCCRA (B,
C)) are as follows. Operation is not guaranteed for any combination that does not exist in the following table.
Moreover, it does not count in emulator mode.
Table 5-1 List of BPC Settings
FUNC[1:0]
MST[3:0]
SLV[1:0]
Target event
01
0000
00
Read access from XBS, DMAC
01
MCH read from XBS, DMAC
10
ICH read from XBS, DMAC
11
Other than MCH/ICH read from XBS, DMAC
0001
00
Read access from XBS
01
MCH read from XBS
10
ICH read from XBS
11
Other than MCH/ICH read from XBS
0100
00
Read access from DMAC
01
MCH read from DMAC
10
ICH read from DMAC
11
Other than MCH/ICH read from DMAC
10
0000
00
Write access from XBS, DMAC
01
MCH write from XBS, DMAC
10
ICH write from XBS, DMAC
11
Other than MCH/ICH write from XBS, DMAC
0001
00
Write access from XBS
01
MCH write from XBS
10
ICH write from XBS
11
Other than MCH/ICH write from XBS
0100
00
Write access from DMAC
01
MCH write from DMAC
10
ICH write from DMAC
11
Other than MCH/ICH write from DMAC
MB91520 Series
MN705-00010-1v0-E
1264