Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
75
- SCSFR2n(n=0 to 11) : Address Base addr + 15
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
CS3
CSLVL
CS3
SCINV
CS3
SPI
CS3
BDS
CS3
L3
CS3
L2
CS3
L1
CS3
L0
1
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit7] CS3CSLVL: Serial chip select level setting bit for chip select 3
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to select the level when the serial
chip select pin 3 is inactive.
CS3CSLVL
Serial chip select pin 3
Serial chip select setting bit
0
Inactive level set to "L"
1
Inactive level set to "H"
Notes:
⋅
This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
⋅
In the slave mode (SCR:MS="0"), setting this bit has no effect.
⋅
When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit6] CS3SCINV: Serial clock invert bit for chip select 3
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to set the serial clock format
when the serial chip select pin 3 is active.
When this bit is set to "0":
⋅
Serial clock output mark level is set to "H".
⋅
Transmission data is output in synchronization with a falling edge of the serial clock in the normal
transfer while it is output in synchronization with a rising edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a rising edge of the serial clock in the normal transfer while it is sampled at
a falling edge of the serial clock in the SPI transfer.
When this bit is set to "1":
⋅
Serial clock output mark level is set to "L".
⋅
Transmission data is output in synchronization with a rising edge of the serial clock in the normal
transfer while it is output in synchronization with a falling edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a falling edge of the serial clock in the normal transfer while it is sampled at
a rising edge of the serial clock in the SPI transfer.
CS3SCINV
Serial chip select pin 3
Serial clock invert bit
0
Mark level "H" format
1
Mark level "L" format
Notes:
⋅
This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
⋅
In the slave mode (SCR:MS="0"), setting this bit has no effect.
⋅
When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit5] CS3SPI: SPI support bit for chip select 3
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to execute an SPI communication
when the serial chip select pin 3 is active.
MB91520 Series
MN705-00010-1v0-E
1388