Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
137
4.5.10.
Baud rate Generator Register: BGR
Baud rate generator register (BGR) sets the division ratio of serial clock.
BGRn(n=3 to 8, 10, 11) : Address Base addr + 1C
H
(Access: Half-word, Word)
15
14
13
12
11
10
9
8
bit
-
BGR[14:8]
-
0
0
0
0
0
0
0
Initial value
RX,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
BGR[7:0]
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15] Undefined
No effect for writing operations.
[bit14] to bit0 BGR (Baud rate GeneratoR): Baud Rate Generator Bit
⋅
These bits set division rate of the serial clock.
⋅
Capable of writing reload value to be counted and reading setup values.
⋅
Reload counter will start counting when a reload value is written.
Notes:
⋅
Write to the baud rate generator (BGR) in 16-bit access mode.
⋅
Configure the baud rate generator register when the EN bit of the ISMK register is "0".
⋅
Configure baud rate regardless of the master mode or slave mode.
⋅
Peripheral clock (PCLK) should be set with 8MHz or more in operating mode 4 (I
2
C mode) and baud
rate generator configured in 400kbps or more should not be used.
MB91520 Series
MN705-00010-1v0-E
1450