Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
5. Operation of UART
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
154
5.2.5.
Start Bit Detection
⋅
The start bit is recognized by the falling edge of the SIN signal in asynchronous mode.
Therefore even if you enable reception operation (SCR:RXE=1), the reception operation will not start
unless the falling edge of the SIN signal is entered.
⋅
When the falling edge of the start bit is detected, the reception reload counter of the baud rate generator
will be reset, a reload will take place again, and the countdown will start. This will always launch a data
sampling aimed at the center of the data.
Figure 5-7 Start Bit Detection
Start bit
Reception
sampling clock
SIN
SIN(Over-
Sampled)
Data bit
SEDGE
(internal signal)
Reload counter
reset
Data sampling
1bit time
MB91520 Series
MN705-00010-1v0-E
1467