Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
206
[2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=1, SCSCR:CSOE=0,
SCSCR:SCAM=0)
Transmission operation
(1) With serial data output enabled (SMR:SOE=1) and transmission operation enabled (SCR:TXE=1),
writing transmission data to TDR sets SSR:TDRE=0.
(2) Transmission operation will be started when serial chip select pin (SCS) becomes active, the
transmission data will be output in synchronization with a rising edge of the serial clock (SCK) input.
(3) Outputting the transmission data in the first bit sets SSR:TDRE=1, and the transmission interrupt is
enabled (SCR:TIE=1), a transmission interrupt request will be generated. At this time, the transmission
data in the second byte can be written.
(4) Transmission operation will be terminated when serial chip select pin (SCS) becomes inactive, and serial
output pin (SOUT) becomes "H".
Reception operation
(1) With serial data output disabled (SMR:SOE=0) and reception operation enabled (SCR:RXE=1), reception
operation will be started when the serial chip select pin (SCS) becomes active, and . reception data will be
sampled at a falling edge of the serial clock input (SCK).
(2) Receiving the last bit sets SSR:RDRF=1 and when the reception interrupt is enabled (SCR:RIE=1), a
reception interrupt request will be generated. At this time, the receive data (RDR) can be read.
(3) Reading the received data (RDR) clears SSR:RDRF to "0".
(4) Reception operation will be terminated when serial chip select pin (SCS) becomes inactive.
Transmission/Reception operation
(1) To perform transmission and reception at the same time, enable serial data output (SMR:SOE=1) and
enable transmission/reception operation (SCR:TXE, RXE=1).
(2) When transmission data is written in TDR, SSR:TDRE=0 is set. When serial chip select pin (SCS) will
become active, transmission/reception operation will be started and the transmission data is output in
synchronization with the rising edge of serial clock (SCK) input. When transmission data of the first bit is
output, SSR:TDRE=1 is set, and when transmission interrupt is enabled (SCR:TIE=1), a transmission
interrupt request is output. At this time, the transmission data of the second byte can be written.
(3) While operating transmission/reception, the reception data will be sampled at a falling edge of the serial
clock input (SCK). Receiving the last bit of receiving data sets SSR:RDRF=1 and when the reception
interrupt is enabled (SCR:RIE=1), a reception interrupt request will be generated. At this time, the receive
data (RDR) can be read. Reading the received data (RDR) clears SSR:RDRF to "0".
(4) Transmission/reception operation will be terminated when serial chip select pin (SCS) becomes inactive,
and serial output pin (SOUT) becomes "H".
MB91520 Series
MN705-00010-1v0-E
1519