Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
235
Operation of Serial Chip Select to Maintain Active (SCSCR:SCAM=1) (Only
Valid in Master Mode (SCR:MS=0))
When the serial chip select active maintaining bit (SCSCR:SCAM) is set to "1" and transmission operation
is started, the serial chip select pin is maintained to be active.
The value of the serial chip select active maintaining bit is checked for each transmission as many as the
number of times set with TBYTE. After the data transmission/receptions are completed as many as the
number of times set with TBYTE, the pin operates as shown below.
⋅
If the serial chip select active maintaining bit is "0", the serial chip select pin turns inactive after the hold
delay time has passed.
⋅
If the serial chip select active maintaining bit is "1" and the serial timer synchronous transmission is used,
the serial chip select pin is maintained to be active. Then, when the serial timer value (STMR) and the
serial timer comparison value (STMCR) are matched, transmission operation is restarted. After that, the
serial chip select pin is maintained to be active until the frame transmission is completed as many as the
number of times set with TBYTE.
⋅
If the serial chip select active maintaining bit is "1" and the serial timer external trigger transmission is
used, the serial chip select pin is maintained to be active. After that, if the edge of the external trigger
which is set with the trigger selection bit (SACSR:TRG1, 0) is detected, the transmission operation is
restarted.
After that, the serial chip select pin is maintained to be active until the frame transmission is completed as
many as the number of times set with TBYTE.
⋅
If the serial chip select active maintaining bit is "1" and the serial timer synchronous transmission and the
external trigger transmission are not used, the serial chip select pin is maintained to be active. At that
time, if the transmission data register (TDR) contains the transmission data (SSR:TDRE=0), the
transmission operation is continued, and the serial chip select pin is maintained to be active until the next
time to send the frames as many as the number of times set with TBYTE.
If the serial chip select active maintaining bit (SCSCR:SCAM) is written to "0", it operates as shown below.
⋅
The serial chip select pin becomes inactive after the data transmission/receptions are completed as many
as the number of times set with TBYTE and the hold delay time has passed.
Under the following conditions, the serial chip select pin becomes inactive when the serial chip select active
maintaining bit (SCSCR:SCAM) is used.
⋅
When SCSCR:SCAM=0 after the transmissions are completed as many as in TBYTE
⋅
When the chip select error occurred (SACSR:CSE=1)
⋅
When transmission is disabled (SCR:TXE=0)
⋅
When software reset is performed (SCR:UPCL=1)
Note:
If the transmission data register (TDR) is empty (SSR:TDRE=1) when the transfer byte error is enabled
(SSR:TBEEN=1) and the data transmission/reception is not completed as many as the number of times set
with TBYTE, the serial chip select pin is not retained and becomes inactive after the hold delay time has
passed, and the chip select error (SACSR:CSE=1) occurs.
MB91520 Series
MN705-00010-1v0-E
1548