Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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Automatic Header Completion Interrupt under Reception
On slave side set in the LIN assist mode (LAMCR:LAMEN=1),when the header reception from LIN Break
to ID Field is completed the flag is set (LAMSR:LAHC=1). If the interrupt is set enabled
(LAMIER:LAHCIE =1), the status interrupt occurs.
to ID Field is completed the flag is set (LAMSR:LAHC=1). If the interrupt is set enabled
(LAMIER:LAHCIE =1), the status interrupt occurs.
Even when LIN bus error/LIN ID parity error/framing error occurs in the LIN assist mode for the ID Field,
the automatic header completion flag is set (LAMSR:LAHC=1). However, reception/transmission
processing of the response stops.
the automatic header completion flag is set (LAMSR:LAHC=1). However, reception/transmission
processing of the response stops.
Figure 7-15 Setting timing of automatic header reception completion flag (LAMSR:LARHC)
LIN bus
LIN Break
LIN Break
delimiter
Sync Field
LAMCR : LAMEN
LIN assist mode processing enable
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP
ID Field
LAMSR : LAHC
It is generated by the reception
completion of ID Field the automatic
header reception completion interruption.
completion of ID Field the automatic
header reception completion interruption.
LIN Checksum Detection Completion Flag Interrupt and Flag Setting Timing
In the assist mode (LAMCR:LAMEN=1), the LIN checksum detection is done on both the side where the
checksum is self-checked and transmitted and the side where the checksum is received When the data of the
setting length (LAMCR:LDL3-0) and the checksum are received, the checksum operation is completed and the
flag is set (LAMSR:LCSC=1). When the interrupt is set enabled (LAMIER:LCSCIE=1), the status interrupt
occurs.
When reception of the checksum is completed, neither the reception checksum value is stored in the RDR
register nor the (SSR:RDRF) is set to "1". When FIFO is used, the received checksum value is not stored in the
reception FIFO
checksum is self-checked and transmitted and the side where the checksum is received When the data of the
setting length (LAMCR:LDL3-0) and the checksum are received, the checksum operation is completed and the
flag is set (LAMSR:LCSC=1). When the interrupt is set enabled (LAMIER:LCSCIE=1), the status interrupt
occurs.
When reception of the checksum is completed, neither the reception checksum value is stored in the RDR
register nor the (SSR:RDRF) is set to "1". When FIFO is used, the received checksum value is not stored in the
reception FIFO
Note:
The result of the checksum operation at this time is not guaranteed when the framing error is detected in the
final data for the setting length (LAMCR:LDL3-0) or when the framing error is detected by the checksum.
final data for the setting length (LAMCR:LDL3-0) or when the framing error is detected by the checksum.
MB91520 Series
MN705-00010-1v0-E
1581