Fujitsu FR81S User Manual
CHAPTER 45: FLASH MEMORY
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
Figure 3-6 Sector Configuration Diagram (MB91F526)
Notes:
⋅
The FixedVector function returns the start address of flash memory + 0x0024 instead of the value written
in address 0x0F_FFFC as the reset vector. For details, see "CHAPTER : FixedVector FUNCTION"
⋅
As for a password setting for enabling on chip debugger (OCD) to start, see "CHAPTER : ON CHIP
DEBUGGER (OCD)". If it is unnecessary to use the security function for on chip debugger (OCD), do
not write anything to the area and keep the default state just after the flash erase (all bits=1).
1024+64kB configuration
Address
0x07_4000
0x07_0000
Lar
ge
s
ec
tor
c
onf
igur
at
ion
uni
t
(64k
B
×16)
S
m
al
l s
ec
tor
c
on
figur
at
ion
uni
t
(8k
B
×8)
bit0 to bit31
bit32 to bit63
SA2(8kB)
SA3(8kB)
SA0(8kB)
SA1(8kB)
SA4(8kB)
SA5(8kB)
SA6(8kB)
SA7(8kB)
0x07_8000
0x07_C000
0x08_0000
SA8(64kB)
SA9(64kB)
0x0A_0000
SA10(64kB)
SA11(64kB)
0x0C_0000
SA12(64kB)
SA13(64kB)
0x0E_0000
SA14(64kB)
SA15(64kB)
0x10_0000
SA16(64kB)
SA17(64kB)
0x12_0000
SA18(64kB)
SA19(64kB)
0x14_0000
SA20(64kB)
SA21(64kB)
0x16_0000
SA22(64kB)
SA23(64kB)
0x17_FFFF
Flash security code
(Second half-word
at the beginning of flash)
(Second half-word
at the beginning of flash)
Password for enabling on-chip
debugger (OCD) startup
(Second word to ninth word
at the beginning of flash)
debugger (OCD) startup
(Second word to ninth word
at the beginning of flash)
Reset vector
(One word of address0x0F_FFFC)
(One word of address0x0F_FFFC)
Interrupt vector table
(Default address of TBR)
(Default address of TBR)
0x0F_FC00
MB91520 Series
MN705-00010-1v0-E
1930