Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
1. Overview
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
Figure 1-1 Diagram of the Clock Generation System
CR oscillation
for WDT1
Sub clock/WDT1(Hardware watchdog)
CR
CR
oscillation circuit
(100KHz)
WDT1
calibration
Source clock (SRCCLK)
Main clock (MCLK)
Sub clock (SBCLK)
Sub clock (SBCLK)
PLL clock (PLLCLK)
* Non spread spectrum clock
PLL/SSCG clock (PLLSSCLK)
* Selectable non spread spectrum
clock or spread spectrum clock
Clock control
Main clock
generation
unit
Main clock (MCLK)
Sub clock
generation
unit
Sub clock (SBCLK)
On-chip debugger (OCD)
Clock generation unit
For DEBUG I/F
PLL clock (M_PCLK)
RTC clock (WATCLK)
To Real Time Clock
For DEBUG I/F
Main clock (M_MCLK)
Watch and Power
management
clock generation unit
PMU clock (PMUCLK)
Source clock select unit
divided by 2
MCLK divided by 2 / SBCLK / PLLSSCLK
PLL/SSCG
clock generation
unit
CAN prescaler clock
CAN prescaler
Clock selection unit
Selector
Peripheral clock (PCLK2)
Peripheral clock
divider
control unit
On-chip bus clock (HCLK)
CPU clock (CCLK)
Peripheral
clock (PCLK1)
External bus clock (TCLK)
Oscillation stop request/
Oscillation stop release request
To Main, Sub, or PLL/SSCG clock generation unit
From Main, Sub, or PLL/SSCG clock generation unit
Oscillation stabilization wait
timer interrupt
Clock divider
control unit
CR
oscillation
divided by 2
MB91520 Series
MN705-00010-1v0-E
165