Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
Figure 3-3 Connection Diagram of Clock (1)-3 PLL/SSCG Clock Generation Unit
Figure 3-4 Connection Diagram of Clock (2) Source Clock Selection Unit
PLL
Timer
PTMCR.
PTIF
POSW
PTMCR.
PTIE
CMONR.
PCRDY
PCEN
SSCG-PLL
PLL
(Non-SSCG)
Divider
Divider
CCPSSELR.
PCSEL
PLLSSCLK
PLL/SSCG clock
1
0
PLLCLK
PLL clock
MCLK
Main clock
Divider
PLLCR.
PDS
CCPSDIVR.
PODS
CCPSDIVR.
SODS
CCPLLFBR.
IDIV
CCSSFBR0
CCSSFBR1
CCSSCCR0
CCSSCCR1
CCCGRCR1
CCCGRCR2
CCCGRCR0
Clock gear
SSCG Enable
PLL Enable
SSCGCLK
SSCG clock
ICR30
Interrupt
PLL timer
CSELR.
PLLCR.
Divider
(1/2)
MCLK2/PLLSSCLK/SBCLK
Source clock
Clock selection contro
l
CSELR.
CKS
CMONR.
CKM
00
01
01
11
PLLSSCLK
PLL/SSCG clock
SBCLK
Sub clock
MCLK
Main clock
MCLK2
Main clock 2 division
MB91520 Series
MN705-00010-1v0-E
168