Fujitsu FR81S User Manual
CHAPTER 47: ON CHIP DEBUGER (OCD)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: ON CHIP DEBUGGER : OCD
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
5.3.3. Clock Reset State Transitions
Clock reset state transitions is shown.
Figure 5-2 Device State
Power on or
low-voltage
detection
Debug
State
PLL
sleep
PLL
RUN
PLL clock mode
Sub clock mode
Sub
sleep
Main clock mode
Sub
stop
Sub
RUN
Main
sleep
Sub watch
mode
Initialization
(SINIT)
Sub watch
mode
(Shutdown)
Sub stop
(Shutdown)
Main
stop
Main stop
(Suhtdown)
Main
watch
mode
Main
RUN
Main
watch mode
(shutdown)
Main
oscillation
wait
Sub
oscillation
wait
Program
reset
(RST)
Main oscillation
stabilization
wait
(RESET)
Setting
initialization
(INIT) *1
Power-on reset or internal low-voltage detection or simultaneously assert of external reset and NMI
Power-on reset release and internal low-voltage detection release and release of simultaneously assert of external reset and NMI
End of oscillation stabilization wait
End of oscillation stabilization wait (if the reset factor is or )
INIT release
RST release
Software reset
Software watchdog reset (including irregular) or software reset (irregular)
External reset input (NMI disabled ) or external low-voltage detection
External reset input (NMI disabled + irregular) or external low-voltage detection (irregular)
○
11
Hardware watchdog reset (including irregular)
○
12
Sleep mode (write instruction)
○
13
Stop mode (write instruction)
○
14
Watch mode (write instruction)
○
15
Interrupt (including ○
16
and ○
17
)
○
16
Interrupt (clock not required)/NMI
○
17
Main timer interrupt/Sub timer interrupt/RTC interrupt
○
18
Switch from main to sub (write instruction)
○
19
Switch from sub to main (write instruction)
○
20
Switch from main to PLL (write instruction)
(21) Switch from PLL to main (write instruction)
(22) Illegal standby mode transition
(23) Illegal standby mode transition detection reset
(24) Stop mode and shutdown (write instruction)
(25) Watch mode and shutdown (write instruction)
(27) RST release (When setting initialization (INIT) is accompanied and the mode command is received normally in the chip reset sequence or when there is a forced break request)
(28) Break return
* : (26) is a missing number.
*
MB91520 Series
MN705-00010-1v0-E
2039