Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.1.1. 16-bit Dead Timer Register (TMRR)
The bit configuration for the 16-bit dad timer register is shown below.
The 16-bit dead timer register (TMRR) holds the reload value of the 16-bit dead timer.
TMRR0: Address 12A0
H
(Access: Half-word, Word)
TMRR1: Address 12A2
H
(Access: Half-word, Word)
TMRR2: Address 12A4
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
Initial values
0
0
0
0
0
0
0
0
Attributes
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
Initial values
0
0
0
0
0
0
0
1
Attributes
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] TR15 to TR00: 16-bit Dead timer reload value bits
TR15 to TR00
Function
16-bit dead timer reload value
⋅
These bits are used to store reload value of the 16-bit dead timer.
⋅
The value of these registers will be reloaded when the 16-bit dead timer starts operating.
⋅
If the value is rewritten to these registers while the timer is active, this new value will become valid
when the timer starts/operates next time.
⋅
In the dead time timer mode, these registers are used to configure non-overlap time.
Non-overlap time = (set value) × selected clock
⋅
In the timer mode, these registers are used to configure GATE time for PPG timer operation.
GATE time = (set value) × selected clock
Note:
When accessing these registers, use a half-word or word access instruction.
Note:
Do not set "0000
H
" to these registers.
MB91520 Series
MN705-00010-1v0-E
2054