Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
DTTI Pin Noise Cancellation Feature
When you set the NRSL of the waveform control register 1 (SIGCR1) to "1", the noise cancellation feature of
the DTTI pin input will become effective. Once the noise cancellation feature becomes effective, the time
required to have the output pins (RTO0 to RTO5) fixed to port control state will be delayed by the 4, 8, 16, or
32 peripheral clock cycles (to be selected by NWS1 and NWS0 of the SIGCR1 register). Since the noise
cancellation circuit uses resources, the input will be invalid even if the DTTI input becomes effective in a
mode where the oscillation stops (i.e. stop mode).
DTTI Interrupt
When "L" level of the DTTI is detected, the DTTI interrupt flag (DTIF of the SIGCR1 register) is set to "1"
after the noise cancellation time has elapsed, and the interrupt request will be transmitted to the interrupt
controller.
Figure 5-17 DTTI Interrupt Timing
Time of noise
cancellation
controlled by
NWS1 and NWS0
bits of SIGCR1
register
"0" writing to DTIF bit of
SIGCR1 register by software
DTTI
DTIF bit of
SIGCR1 register
Note:
If the value of NWS1 and NWS0 bits of the SIGCR1 register changes during the noise cancellation time,
the greater noise cycle value (NWS1, NWS0) will become effective.
DTIF of the SIGCR1 register can be cleared by software only.
MB91520 Series
MN705-00010-1v0-E
2092