Fujitsu FR81S User Manual
CHAPTER 49: BUS DIAGNOSIS FUNCTION
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : BUS DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
Bus Diagnosis Operation Flow
The operation flow of the bus diagnosis is shown below.
(1) At register reading
Start
Address output from the CPU
Calculate and output parity
CPU side
Data output from resources
Calculate and output parity
Parity error in address 31 to 24?
AER [0] <- 1, BUSADR <- Address, RDWR <- 0
Resource side
End
(AER [3:0] =0000 and DER [3:0] =0000)?
CPU side: Parity Gen/Chk close to the CPU
Resource side: Parity Gen/Chk close to the resource
Parity error in address 23 to 16?
AER [1] <- 1, BUSADR <- Address, RDWR <- 0
Parity error in address 7 to 0?
AER [3] <- 1, BUSADR <- Address, RDWR <- 0
Parity error in address 15 to 8?
AER [2] <- 1, BUSADR <- Address, RDWR <- 0
(AER [3:0] ==0 and DER [3:0] ==0)?
(Error in address and DER[3:0]==0)?
Parity error in data 31 to 24?
DER [0] <- 1, BUSADR <- Address, RDWR <- 0
Parity error in data 23 to 16?
DER [1] <- 1, BUSADR <- Address, RDWR <- 0
Parity error in data 15 to 8?
DER [2] <- 1, BUSADR <- Address, RDWR <- 0
Parity error in data 7 to 0?
DER [3] <- 1, BUSADR <- Address, RDWR <- 0
CPU side
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
MB91520 Series
MN705-00010-1v0-E
2118