Fujitsu FR81S User Manual
APPENDIX
A. I/O Map
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
Address
Address offset value / Register name
Block
+0
+1
+2
+3
000240
H
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
Free-run Timer 3
32-bit FRT
000244
H
TCDT3 [R/W] W
00000000 00000000 00000000 00000000
000248
H
TCCSH3 [R/W]
B,H,W
0-----00
TCCSL3 [R/W]
B,H,W
-1-00000
―
―
00024C
H
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
Free-run Timer 4
32-bit FRT
000250
H
TCDT4 [R/W] W
00000000 00000000 00000000 00000000
000254
H
TCCSH4 [R/W]
B,H,W
0-----00
TCCSL4 [R/W]
B,H,W
-1-00000
―
―
000258
H
to
0002C0
H
―
―
―
―
Reserved
0002C4
H
to
0002FC
H
―
―
―
―
Reserved
000300
H
to
00030C
H
―
―
―
―
Reserved
000310
H
―
―
MPUCR [R/W] H
000000-0 ----0100
MPU [S]
(Only CPU core
can access this
area)
000314
H
―
―
―
―
000318
H
―
00031C
H
―
―
―
000320
H
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000324
H
―
―
DPVSR [R/W] H
-------- 00000--0
000328
H
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00032C
H
―
―
DESR [R/W] H
-------- 00000--0
000330
H
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000334
H
―
―
PACR0 [R/W] H
000000-0 00000--0
000338
H
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00033C
H
―
―
PACR1 [R/W] H
000000-0 00000--0
MB91520 Series
MN705-00010-1v0-E
2216