Fujitsu FR81S User Manual

CHAPTER 8: DMA CONTROLLER (DMAC)

3. Configuration

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : DMA CONTROLLER (DMAC)

FUJITSU SEMICONDUCTOR CONFIDENTIAL

3. Configuration

This section explains the configuration of the DMA controller (DMAC).

Figure 3-1 Block Diagram

Generation and

clear circuit of DMA

transfer request

caused by interrupt

Peripheral

Interrupt
controller

Interrupt request

Interrupt clear request

CPU

FLASH

RAM

Peripheral
bus bridge

On-chip bus

peripheral

On-chip bus

Master interface

Slave interface

Data

buffer

control

Read engine
and transfer
destination
Write transfer
destination

Determining

priorities

Accept
transfer
request

DMAC

Transfer
acceptance/
Transfer
termination

Accept
transfer
request

MB91520 Series

MN705-00010-1v0-E

304