Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
32
4.23. DMA Request Clear Register 24 : ICSEL24 (Interrupt
Clear SELect register 24)
The bit configuration of DMA request clear register 24 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #49).
ICSEL24: Address 0438
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
MFS_SEL1[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] MFS_SEL1[1:0] (MFS_Selection1) : Interrupt clear selection bits for MFS ch.9
(transmission completion) / OCU0 / OCU1
MFS_SEL1[1:0]
Clear target
00
Multi-function serial ch.9 reception completion
01
16-bit OCU0
10
16-bit OCU1
11
Reserved (Does not clear any)
Note:
Setting MFS_SEL1[1:0]= "11" is prohibited. During this setting, no interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
377